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Jinn-Shyan Wang

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Yuan-Hua Chu

> Home > Persons > Jinn-Shyan Wang

Publications

2014
[c59]
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  dblp key:
  - conf/asscc/ChengWCCSCY14
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  - https://dblp.org/rec/conf/asscc/ChengWCCSCY14
Chun-Yuan Cheng, Jinn-Shyan Wang, Pei-Yuan Chou, Shiou-Ching Chen, Chi-Tien Sun, Yuan-Hua Chu, Tzu-Yi Yang:
A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm² all-digital delay-locked loop in 65-nm CMOS. A-SSCC 2014: 361-364
[c58]
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  dblp key:
  - conf/hotchips/HuangCCTHPCCLW14
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  - https://dblp.org/rec/conf/hotchips/HuangCCTHPCCLW14
Chung-Hsun Huang, Wei-Jen Chen, Keng-Jui Chang, Yi-Hsuan Ting, Keng-Chang Hsu, Yu-Fu Pan, Chao-Chun Chen, Yuan-Hua Chu, Tay-Jyi Lin, Jinn-Shyan Wang:
Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET). Hot Chips Symposium 2014: 1
2013
[c56]
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  - conf/isscc/LinCCCWSCLGCCCCSJIWW13
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  - https://dblp.org/rec/conf/isscc/LinCCCWSCLGCCCCSJIWW13
Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang:
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC 2013: 158-159
2006
[c33]
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  dblp key:
  - conf/iscas/WangCYC06
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  - https://dblp.org/rec/conf/iscas/WangCYC06
Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu:
Design of STR level converters for SoCs using the multi-island dual-VDD design technique. ISCAS 2006
1995
[c1]
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  dblp key:
  - conf/iscas/HuangWCWCW95
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Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu:
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. ISCAS 1995: 1572-1575

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