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Arnaud Virazel
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Publications
- 2022
- [p1]Marcello Traiola, Bastien Deveautour, Alberto Bosio, Patrick Girard, Arnaud Virazel:
Test and Reliability of Approximate Hardware. Approximate Computing 2022: 233-266 - 2021
- [c141]Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels:
Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*. ETS 2021: 1-10 - [c138]Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard:
Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing. IOLTS 2021: 1-7 - 2020
- [j34]Bastien Deveautour, Arnaud Virazel, Patrick Girard, Valentin Gherman:
On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits. J. Electron. Test. 36(1): 33-46 (2020) - [c133]Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard:
QAMR: an Approximation-Based Fully Reliable TMR Alternative for Area Overhead Reduction. ETS 2020: 1-6 - [c131]Florence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzèrho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea, T. Vayssade, Arnaud Virazel:
Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. IOLTS 2020: 1-4 - 2018
- [c124]Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman:
Is aproximate computing suitable for selective hardening of arithmetic circuits? DTIS 2018: 1-6 - 2017
- [j31]Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda:
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. J. Electron. Test. 33(1): 25-36 (2017) - 2016
- [c114]Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda:
A low-cost susceptibility analysis methodology to selectively harden logic circuits. ETS 2016: 1-2
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