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Renato P. Ribas
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Publications
- 2018
- [j16]Augusto Neutzling, Mayler G. A. Martins, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
A Simple and Effective Heuristic Method for Threshold Logic Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 1023-1036 (2018) - 2015
- [j12]Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas:
Factored Forms for Memristive Material Implication Stateful Logic. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 267-278 (2015) - [c71]Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis:
Enhanced Spin-Diode Synthesis Using Logic Sharing. DSD 2015: 218-224 - [c68]Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. ICCD 2015: 680-687 - [c65]Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas:
Improved logic synthesis for memristive stateful logic using multi-memristor implication. ISCAS 2015: 181-184 - [c64]Mayler G. A. Martins, Jody Maick Matos, Renato P. Ribas, André Inácio Reis, Guilherme Schlinker, Lucio Rech, Jens Michelsen:
Open Cell Library in 15nm FreePDK Technology. ISPD 2015: 171-178 - 2014
- [c61]Matheus T. Moreira, Augusto Neutzling, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas, Ney Calazans:
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? ASYNC 2014: 53-60 - [c60]Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
A constructive approach for threshold logic circuit synthesis. ISCAS 2014: 385-388 - [c58]Iuri A. C. Gomes, Mayler G. A. Martins, Fernanda Lima Kastensmidt, André Inácio Reis, Renato P. Ribas, Sylvain P. Novales:
Methodology for achieving best trade-off of area and fault masking coverage in ATMR. LATW 2014: 1-6 - 2013
- [c52]Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
Iterative remapping respecting timing constraints. ISVLSI 2013: 236-241 - [c49]Vinicius Callegaro, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Read-polarity-once Boolean functions. SBCCI 2013: 1-6 - [c46]Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis:
Spin diode network synthesis using functional composition. SBCCI 2013: 1-6 - [c45]Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Synthesis of threshold logic gates to nanoelectronics. SBCCI 2013: 1-6 - 2012
- [c41]Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Functional composition: A new paradigm for performing logic synthesis. ISQED 2012: 236-242 - [c39]Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
KL-cut based digital circuit remapping. NORCHIP 2012: 1-4 - 2011
- [c33]Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
Efficient method to compute minimum decision chains of Boolean functions. ACM Great Lakes Symposium on VLSI 2011: 419-422 - 2010
- [c24]Mayler G. A. Martins, Leomar S. da Rosa Jr., Anders B. Rasmussen, Renato P. Ribas, André Inácio Reis:
Boolean factoring with multi-objective goals. ICCD 2010: 229-234
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