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Masao Yanagisawa
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Publications
- 2017
- [c83]Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa:
Effective write-reduction method for MLC non-volatile memory. ISCAS 2017: 1-4 - 2015
- [j53]Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa:
ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2494-2504 (2015) - [c63]Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa:
A bit-write reduction method based on error-correcting codes for non-volatile memories. ASP-DAC 2015: 496-501 - 2013
- [c44]Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi:
Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. ASICON 2013: 1-4 - 2006
- [j13]Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki:
Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 996-1004 (2006) - [c17]Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki:
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC 2006: 653-658 - 2005
- [c14]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura:
Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium 2005: 386-389 - 2004
- [c9]Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium 2004: 432-437 - 2003
- [j9]Youhua Shi, Zhe Zhang, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki:
A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3056-3062 (2003)
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