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Daniel Gajski
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Publications
- 2009
- [j46]Andreas Gerstlauer, Christian Haubelt, Andy D. Pimentel, Todor P. Stefanov, Daniel D. Gajski, Jürgen Teich:
Electronic System-Level Synthesis Methodologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1517-1530 (2009) - 2008
- [j45]Rainer Dömer, Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Lukai Cai, Haobo Yu, Samar Abdi, Daniel D. Gajski:
System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design. EURASIP J. Embed. Syst. 2008 (2008) - [j43]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski:
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 466-475 (2008) - [c157]Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Daniel Gajski, Atsushi Nakamura, Dai Araki, Yuuji Nishihara:
Specify-explore-refine (SER): from specification to implementation. DAC 2008: 586-591 - 2007
- [j42]Andreas Gerstlauer, Dongwan Shin, Junyu Peng, Rainer Dömer, Daniel Gajski:
Automatic Layer-Based Generation of System-On-Chip Bus Communication Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1676-1687 (2007) - [c147]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski:
An Interactive Design Environment for C-based High-Level Synthesis. IESS 2007: 135-144 - 2006
- [c142]Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dömer, Daniel D. Gajski:
Automatic generation of transaction level models for rapid design space exploration. CODES+ISSS 2006: 64-69 - 2005
- [c137]Andreas Gerstlauer, Dongwan Shin, Rainer Dömer, Daniel D. Gajski:
System-level communication modeling for network-on-chip synthesis. ASP-DAC 2005: 45-48 - [c135]Lukai Cai, Andreas Gerstlauer, Daniel Gajski:
Multi-metric and multi-entity characterization of applications for early system design exploration. ASP-DAC 2005: 944-947 - [c131]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski:
Automatic network generation for system-on-chip communication design. CODES+ISSS 2005: 255-260 - [c125]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski:
Automatic Generation of Communication Architectures. IESS 2005: 179-188 - 2004
- [c117]Lukai Cai, Andreas Gerstlauer, Daniel Gajski:
Retargetable profiling for rapid, early system-level design space exploration. DAC 2004: 281-286 - 2003
- [c112]Haobo Yu, Andreas Gerstlauer, Daniel Gajski:
RTOS scheduling in transaction level models. CODES+ISSS 2003: 31-36 - [c110]Andreas Gerstlauer, Haobo Yu, Daniel Gajski:
RTOS Modeling for System Level Design. DATE 2003: 10130-10135 - [p1]Andreas Gerstlauer, Haobo Yu, Daniel D. Gajski:
RTOS Modeling for System Level Design. Embedded Software for SoC 2003: 55-68 - 2002
- [c108]Slim Ben Saoud, Daniel D. Gajski, Andreas Gerstlauer:
Co-design of embedded controllers for power electronics and electric systems. ISIC 2002: 379-383 - [c104]Daniel Gajski, Andreas Gerstlauer:
System-Level Abstraction Semantics. ISSS 2002: 231-236 - [c103]Slim Ben Saoud, Daniel D. Gajski, Andreas Gerstlauer:
Seamless approach for the design of control systems for power electronics and electric drives. SMC 2002: 6 - 2001
- [b2]Andreas Gerstlauer, Rainer Dömer, Junyu Peng, Daniel D. Gajski:
System Design - A Practical Guide with SpecC. Springer 2001, ISBN 978-0-7923-7387-2, pp. 1-255 - 2000
- [c92]Achim Rettberg, Franz J. Rammig, Andreas Gerstlauer, Daniel Gajski, Wolfram Hardt, Bernd Kleinjohann:
The Specification Language SpecC within the PARADISE Design Environment. DIPES 2000: 111-120
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