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ORCIDShinichi Yamagiwa
- > Home > Persons > Shinichi Yamagiwa
Publications
- 2023
[c45]Taiki Kato, Shinichi Yamagiwa, Koichi Wada:
Toward Parallelization Technique for Stream-based Lossless Data Compression. IEEE Big Data 2023: 2667-2672- 2022
- [j17]Danhe Tian
, Shinichi Yamagiwa, Koichi Wada:
Heuristic Method for Minimizing Model Size of CNN by Combining Multiple Pruning Techniques. Sensors 22(15): 5874 (2022) - 2016
- [c38]Guyue Wang, Koichi Wada, Shinichi Yamagiwa:
Performance Evaluation of Parallelizing Algorithm Using Spanning Tree for Stream-Based Computing. CANDAR 2016: 497-503 - 2015
- [j11]Shinichi Yamagiwa, Guyue Wang, Koichi Wada:
Development of an Algorithm for Extracting Parallelism and Pipeline Structure from Stream-based Processing flow with Spanning Tree. Int. J. Netw. Comput. 5(1): 159-179 (2015) - 2014
- [c34]Guyue Wang, Shinichi Yamagiwa, Koichi Wada:
Parallelism Extraction Algorithm from Stream-Based Processing Flow Applying Spanning Tree. IPDPS Workshops 2014: 632-641 - 2013
- [c29]Shinichi Yamagiwa, Ryoyu Watanabe, Koichi Wada:
Operation Synchronization Technique on Pipeline-Based Hardware Synthesis Applying Stream-Based Computing Framework. IPDPS Workshops 2013: 761-770 - 2011
- [j7]Pablo Lamilla Álvarez, Shinichi Yamagiwa, Masahiro Arai, Koichi Wada:
A Uniform Platform to Support Multigenerational GPUs for High Performance Stream-based Computing. Int. J. Netw. Comput. 1(2): 230-243 (2011) - [j6]Shinichi Yamagiwa, Koichi Wada:
Performance impact on resource sharing among multiple CPU- and GPU-based applications. Int. J. Parallel Emergent Distributed Syst. 26(4): 313-329 (2011) - [c24]Masahiro Arai, Koichi Wada, Shinichi Yamagiwa:
Improving Stream Buffer Management of Stream-Based Computing Platform on GPU. ICNC 2011: 307-312 - [c20]Pablo Lamilla Álvarez, Shinichi Yamagiwa, Masahiro Arai, Koichi Wada:
Elimination Techniques of Redundant Data Transfers Among GPUs and CPU on Recursive Stream-Based Applications. IPDPS Workshops 2011: 708-715 - 2010
- [c18]Shinichi Yamagiwa, Masahiro Arai, Koichi Wada:
Design and Implementation of a Uniform Platform to Support Multigenerational GPU Architectures for High Performance Stream-Based Computing. ICNC 2010: 249-255 - 2009
- [c17]Shinichi Yamagiwa, Koichi Wada:
Performance study of interference on GPU and CPU resources with multiple applications. IPDPS 2009: 1-8 - 2008
- [c13]Shinichi Yamagiwa, Koichi Wada, Leonel Sousa:
Heuristic Optimization Methods for Improving Performance of Recursive General Purpose Applications on GPUs. ISPDC 2008: 325-332 - 2006
- [j2]Shinichi Yamagiwa, Leonel Sousa, Kevin Ferreira, Keiichi Aoki, Masaaki Ono, Koichi Wada:
Maestro2: Experimental Evaluation of Communication Performance Improvement Techniques in the Link Layer. J. Interconnect. Networks 7(2): 295-318 (2006) - 2005
- [c8]Shinichi Yamagiwa, Keiichi Aoki, Koichi Wada:
Active Zero-copy: A performance study of non-deterministic messaging. ISPDC 2005: 325-332 - [c7]Keiichi Aoki, Koichi Wada, Masaaki Ono, Shinichi Yamagiwa:
High Performance Message Passing Library for Maestro2 Cluster Network. Parallel and Distributed Computing and Networks 2005: 199-204 - [c6]Shinichi Yamagiwa, Keiichi Aoki, Koichi Wada:
Performance Enhancement of Inter-Cluster Communication with Software-based Data Compression Link Layer. IASTED PDCS 2005: 516-523 - 2004
- [c4]Shinichi Yamagiwa, Kevin Ferreira, Luís Miguel Campos, Keiichi Aoki, Masaaki Ono, Koichi Wada, Munehiro Fukuda, Leonel Sousa:
On the performance of Maestro2 high performance network equipment, using new improvement techniques. IPCCC 2004: 103-110 - [c3]Kevin Ferreira, Shinichi Yamagiwa, Leonel Sousa, Keiichi Aoki, Koichi Wada, Luís Miguel Campos:
Distributed Shared Memory System Based on the Maestro2 High Performance Cluster Network. ISPDC/HeteroPar 2004: 91-96 - 2002
- [j1]Koichi Wada, Shinichi Yamagiwa, Munehiro Fukuda:
High Performance Network of PC Cluster Maestro. Clust. Comput. 5(1): 33-42 (2002) - 2000
- [c2]Shinichi Yamagiwa, Munehiro Fukuda, Koichi Wada:
Design and Performance of Maestro Cluster Network. CLUSTER 2000: 35-44 - 1998
- [c1]Shinichi Yamagiwa, Masaaki Ono, Takeshi Yamazaki, Pusit Kulkasem, Masayuki Hirota, Koichi Wada:
Maestro-Link: A High Performance Interconnect for PC Cluster. FPL 1998: 421-425
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