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Salvador Petit
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Publications
- 2015
- [j18]Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
Design of Hybrid Second-Level Caches. IEEE Trans. Computers 64(7): 1884-1897 (2015) - 2014
- [j16]Salvador Petit, Rafael Ubal, Julio Sahuquillo, Pedro López:
Efficient Register Renaming and Recovery for High-Performance Processors. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1506-1514 (2014) - 2013
- [j14]Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
Hardware-Based Generation of Independent Subtraces of Instructions in Clustered Processors. IEEE Trans. Computers 62(5): 944-955 (2013) - [c36]Vicente Lorente, Alejandro Valero, Julio Sahuquillo, Salvador Petit, Ramon Canal, Pedro López, José Duato:
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. DATE 2013: 83-88 - 2012
- [j13]Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
Combining recency of information with selective random and a victim cache in last-level caches. ACM Trans. Archit. Code Optim. 9(3): 16:1-16:20 (2012) - [j12]Alejandro Valero, Salvador Petit, Julio Sahuquillo, Pedro López, José Duato:
Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches. IEEE Trans. Computers 61(9): 1231-1242 (2012) - [j10]Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, David R. Kaeli:
A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions. IEEE Trans. Parallel Distributed Syst. 23(8): 1361-1368 (2012) - [j9]Alejandro Valero, Julio Sahuquillo, Vicente Lorente, Salvador Petit, Pedro López, José Duato:
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 1108-1117 (2012) - [c32]Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
Analyzing the optimal ratio of SRAM banks in hybrid caches. ICCD 2012: 297-302 - 2011
- [c28]Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour. PACT 2011: 214 - [c25]Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
MRU-Tour-based Replacement Algorithms for Last-Level Caches. SBAC-PAD 2011: 112-119 - 2010
- [c24]Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
Exploiting subtrace-level parallelism in clustered processors. PACT 2010: 555-556 - [c21]Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, David R. Kaeli:
Out-of-order retirement of instructions in sequentially consistent multiprocessors. ICCD 2010: 1-8 - 2009
- [j7]Rafael Ubal, Julio Sahuquillo, Salvador Petit, Houcine Hassan, Pedro López:
Power Reduction In Advanced Embedded IPC Processors. Intell. Autom. Soft Comput. 15(3): 495-507 (2009) - [j6]Salvador Petit Marti, Julio Sahuquillo Borrás, Pedro Juan López Rodríguez, Rafael Ubal Tena, José Duato Marín:
A Complexity-Effective Out-of-Order Retirement Microarchitecture. IEEE Trans. Computers 58(12): 1626-1639 (2009) - [c18]Salvador Petit, Rafael Ubal, Julio Sahuquillo, Pedro López, José Duato:
An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions. DSD 2009: 635-642 - [c17]Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López:
Paired ROBs: A Cost-Effective Reorder Buffer Sharing Strategy for SMT Processors. Euro-Par 2009: 309-320 - [c16]Salvador Petit, Rafael Ubal, Julio Sahuquillo, Pedro López:
A power-aware hybrid RAM-CAM renaming mechanism for fast recovery. ICCD 2009: 150-157 - [c14]Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López, José Duato:
An hybrid eDRAM/SRAM macrocell to implement first-level data caches. MICRO 2009: 213-221 - 2008
- [c13]Noel Tomás, Julio Sahuquillo, Salvador Petit, Pedro López:
Reducing the Number of Bits in the BTB to Attack the Branch Predictor Hot-Spot. Euro-Par 2008: 317-326 - [c11]Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures. IPDPS 2008: 1-11 - 2007
- [c10]Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors. PACT 2007: 429 - [c9]Rafael Ubal, Julio Sahuquillo, Salvador Petit, Houcine Hassan, Pedro López:
Leakage Current Reduction in Data Caches on Embedded Systems. IPC 2007: 45-50 - [c8]Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López:
Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors. SBAC-PAD 2007: 62-68 - 2006
- [c7]Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López:
Applying the zeros switch-off technique to reduce static energy in data caches. SBAC-PAD 2006: 133-140
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