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Dominique Borrione
- > Home > Persons > Dominique Borrione
Publications
- 2014
- [c53]Zeineb Bel Hadj Amor, Laurence Pierre, Dominique Borrione:
A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow. VLSI-SoC 2014: 1-6 - 2009
- [j9]Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz:
A Formal Approach to the Verification of Networks on Chip. EURASIP J. Embed. Syst. 2009 (2009) - [c49]Florent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre:
High-level symbolic simulation for automatic model extraction. DDECS 2009: 218-221 - 2008
- [c44]Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz:
Executable formal specification and validation of NoC communication infrastructures. SBCCI 2008: 176-181 - 2007
- [c41]Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz:
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. NOCS 2007: 127-136 - 2000
- [j5]Dominique Borrione, Julia Dushina, Laurence V. Pierre:
A compositional model for the functional verification of high-level synthesis results. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 526-530 (2000) - 1998
- [c15]Dominique Borrione, Julia Dushina, Laurence Pierre:
Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis. SBCCI 1998: 99-102 - 1992
- [j2]Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem:
Formal Verification of VHDL Descriptions in the Prevail Environment. IEEE Des. Test Comput. 9(2): 42-56 (1992)
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