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Howard C. Luong
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Publications
- 2019
- [j58]Zhiqiang Huang, Howard C. Luong:
An 82-107.6-GHz Integer-N ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta-Sigma TDC. IEEE J. Solid State Circuits 54(2): 358-367 (2019) - [c57]Xiaolong Liu, Zhiqiang Huang, Jun Yin, Howard C. Luong:
Magnetic-Tuning Millimeter-Wave CMOS Oscillators (Invited Paper). CICC 2019: 1-8 - 2018
- [j55]Zhiqiang Huang, Bingwei Jiang, Howard C. Luong:
A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7): 2118-2126 (2018) - [c55]Zhiqiang Huang, Howard Cam Luong:
An 82-to-108GHz -181dB-FOMT ADPLL employing a DCO with split-transformer and dual-path switched-capacitor ladder and a clock-skew-sampling delta-sigma TDC. ISSCC 2018: 260-262 - 2017
- [j50]Zhiqiang Huang, Howard Cam Luong:
Design and Analysis of Millimeter-Wave Digitally Controlled Oscillators With C-2C Exponentially Scaling Switched-Capacitor Ladder. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(6): 1299-1307 (2017) - 2016
- [c47]Zhiqiang Huang, Bingwei Jiang, Lianming Li, Howard Cam Luong:
2.3 A 4.2µs-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL. ISSCC 2016: 40-41 - 2015
- [c44]Zhiqiang Huang, Howard Cam Luong, Baoyong Chi, Zhihua Wang, Haikun Jia:
25.6 A 70.5-to-85.5GHz 65nm phase-locked loop with passive scaling of loop filter. ISSCC 2015: 1-3 - [c43]Zhiqiang Huang, Howard Cam Luong:
A dithering-less 54.79-to-63.16GHz DCO with 4-Hz frequency resolution using an exponentially-scaling C-2C switched-capacitor ladder. VLSIC 2015: 234-
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