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Shinichi Yasuda

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Shinobu Fujita

> Home > Persons > Shinichi Yasuda

Publications

2017
[j2]
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  - journals/tcas/TanamotoYTF17
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  - https://dblp.org/rec/journals/tcas/TanamotoYTF17
Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita:
Physically Unclonable Function Using an Initial Waveform of Ring Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 64-II(7): 827-831 (2017)
[i2]
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  dblp key:
  - journals/corr/TanamotoTSKYMFM17
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  - https://dblp.org/rec/journals/corr/TanamotoTSKYMFM17
Tetsufumi Tanamoto, Satoshi Takaya, Nobuaki Sakamoto, Hirotsugu Kasho, Shinichi Yasuda, Takao Marukame, Shinobu Fujita, Yuichiro Mitani:
Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology. CoRR abs/1703.00073 (2017)
2016
[i1]
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  - journals/corr/TanamotoYTF16
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Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita:
Physically Unclonable Function using Initial Waveform of Ring Oscillators. CoRR abs/1605.03290 (2016)
2012
[c8]
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  dblp key:
  - conf/ipps/IkegamiANYOF12
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  - https://dblp.org/rec/conf/ipps/IkegamiANYOF12
Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Masato Oda, Shinobu Fujita:
Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation. IPDPS Workshops 2012: 213-220
2010
[c7]
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  dblp key:
  - conf/dac/FujitaYLCAW10
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  - https://dblp.org/rec/conf/dac/FujitaYLCAW10
Shinobu Fujita, Shinichi Yasuda, Daesung Lee, Xiangyu Chen, Deji Akinwande, H.-S. Philip Wong:
Detachable nano-carbon chip with ultra low power. DAC 2010: 631-632
[c6]
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  dblp key:
  - conf/fpga/YasudaTIKANF10
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Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita:
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). FPGA 2010: 291
2009
[c5]
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  - conf/iscas/FujitaANYT09
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Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto:
Perspectives and Issues in 3D-IC from Designers' Point of View. ISCAS 2009: 73-76
2008
[c4]
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  dblp key:
  - conf/isscc/MatsumotoYOITF08
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Mari Matsumoto, Shinichi Yasuda, Ryuji Ohba, Kazutaka Ikegami, Tetsufumi Tanamoto, Shinobu Fujita:
1200μm² Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application. ISSCC 2008: 414-415
2007
[c3]
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  - conf/cicc/YasudaF07
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Shinichi Yasuda, Shinobu Fujita:
Compact Fault Recovering Flip-Flop with Adjusting Clock Timing Triggered by Error Detection. CICC 2007: 721-724
2006
[c2]
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  - conf/isvlsi/OhbaMMYTUF06
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Ryuji Ohba, Daisuke Matsushita, Koichi Muraoka, Shinichi Yasuda, Tetsufumi Tanamoto, Ken Uchida, Shinobu Fujita:
Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation. ISVLSI 2006: 231-236
2005
[c1]
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  - conf/esscirc/YasudaTOANF05
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Shinichi Yasuda, Tetsufumi Tanamoto, Ryuji Ohba, Keiko Abe, Hanae Nozaki, Shinobu Fujita:
Physical random number generators for cryptographic application in mobile devices. ESSCIRC 2005: 399-402
2004
[j1]
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  - journals/jssc/YasudaSTOUF04
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Shinichi Yasuda, Hideki Satake, Tetsufumi Tanamoto, Ryuji Ohba, Ken Uchida, Shinobu Fujita:
Physical random number generator based on MOS structure after soft breakdown. IEEE J. Solid State Circuits 39(8): 1375-1377 (2004)

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