Shyh-Jye Jou

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Ching-Da Chan

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Publications

2016
[c71]
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Wei-Chang Liu, Ching-Da Chan, Shuo-An Huang, Chi-Wei Lo, Chia-Hsiang Yang, Shyh-Jye Jou:
Error-resilient sequential cells with successive time borrowing for stochastic computing. ICASSP 2016: 6545-6549
2015
[j39]
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Wei-Chang Liu, Ting-Chen Wei, Ya-Shiue Huang, Ching-Da Chan, Shyh-Jye Jou:
All-Digital Synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 545-553 (2015)
2014
[c61]
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Wei-Chang Liu, Fu-Chun Yeh, Chia-Yi Wu, Ting-Chen Wei, Ya-Shiue Huang, Shen-Jui Huang, Ching-Da Chan, Shyh-Jye Jou, Sau-Gee Chen:
An IEEE 802.15.3c/802.11ad compliant SC/OFDM dual-mode baseband receiver for 60 GHz Band. ISCAS 2014: 1006-1009
2013
[j25]
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Wei-Chang Liu, Fu-Chun Yeh, Ting-Chen Wei, Ching-Da Chan, Shyh-Jye Jou:
A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(10): 2730-2739 (2013)
[c56]
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Wei-Chang Liu, Fu-Chun Yeh, Ting-Chen Wei, Ya-Shiue Huang, Tai-Yang Liu, Shen-Jui Huang, Ching-Da Chan, Shyh-Jye Jou, Sau-Gee Chen:
A SC/HSI dual-mode baseband receiver with frequency-domain equalizer for IEEE 802.15.3c. ISCAS 2013: 793-796
[c50]
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Ching-Da Chan, Wei-Chang Liu, Chia-Hsiang Yang, Shyh-Jye Jou:
Power and area reduction in multi-stage addition using operand segmentation. VLSI-DAT 2013: 1-4

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