Yale N. Patt

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Eiman Ebrahimi

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Publications

2016
[c144]
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Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt:
Accelerating Dependent Cache Misses with an Enhanced Memory Controller. ISCA 2016: 444-455
2012
[j50]
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Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt:
Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multicore Memory Systems. ACM Trans. Comput. Syst. 30(2): 7:1-7:35 (2012)
[c136]
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  - conf/micro/MiftakhutdinovEP12
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Rustam Miftakhutdinov, Eiman Ebrahimi, Yale N. Patt:
Predicting Performance Impact of DVFS for Realistic Memory Systems. MICRO 2012: 155-165
[c134]
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  - conf/sbac-pad/AlvesKENVNP12
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Marco A. Z. Alves, Khubaib, Eiman Ebrahimi, Veynu Narasiman, Carlos Villavieja, Philippe Olivier Alexandre Navaux, Yale N. Patt:
Energy Savings via Dead Sub-Block Prediction. SBAC-PAD 2012: 51-58
2011
[c133]
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  - conf/isca/EbrahimiLMP11
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Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt:
Prefetch-aware shared resource management for multi-core systems. ISCA 2011: 141-152
[c131]
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  - conf/micro/EbrahimiMFLJMP11
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Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, José A. Joao, Onur Mutlu, Yale N. Patt:
Parallel application memory scheduling. MICRO 2011: 362-373
2010
[c129]
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  - conf/asplos/EbrahimiLMP10
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Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt:
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. ASPLOS 2010: 335-346
2009
[c125]
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  - conf/hpca/EbrahimiMP09
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Eiman Ebrahimi, Onur Mutlu, Yale N. Patt:
Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems. HPCA 2009: 7-17
[c122]
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  - conf/micro/EbrahimiMLP09
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Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt:
Coordinated control of multiple prefetchers in multi-core systems. MICRO 2009: 316-326

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