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José L. Núñez-Yáñez
- > Home > Persons > José L. Núñez-Yáñez
Publications
- 2021
- [j41]José L. Núñez-Yáñez, Mohammad Hosseinabady:
Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks. Array 12: 100101 (2021) - 2020
- [j37]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1272-1285 (2020) - [c58]Mohammad Hosseinabady, José L. Núñez-Yáñez:
Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System. PARMA-DITAM@HiPEAC 2020: 1:1-1:6 - [c57]José L. Núñez-Yáñez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady:
Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling. PARMA-DITAM@HiPEAC 2020: 2:1-2:6 - [i8]José L. Núñez-Yáñez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady:
Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling. CoRR abs/2006.12176 (2020) - [i7]Kris Nikov, Mohammad Hosseinabady, Rafael Asenjo, Andrés Rodríguez, Angeles G. Navarro, José L. Núñez-Yáñez:
High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip. CoRR abs/2008.08883 (2020) - 2019
- [j33]José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran:
Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. 75(8): 4078-4095 (2019) - [j32]José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran:
Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. 75(8): 4096-4097 (2019) - [i5]Mohammad Hosseinabady, Mohd Amiruddin Bin Zainol, José L. Núñez-Yáñez:
Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities. CoRR abs/1901.06331 (2019) - 2018
- [j30]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Dynamic Energy Management of FPGA Accelerators in Embedded Systems. ACM Trans. Embed. Comput. Syst. 17(3): 63:1-63:26 (2018) - [c51]Sam Amiri, Mohammad Hosseinabady, Simon McIntosh-Smith, José L. Núñez-Yáñez:
Multi-precision convolutional neural networks on heterogeneous hardware. DATE 2018: 419-424 - [c50]Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, José L. Núñez-Yáñez:
Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. FPL 2018: 376-380 - [i2]José L. Núñez-Yáñez, Mohammad Hosseinabady, Moslem Amiri, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia:
Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems. CoRR abs/1802.03316 (2018) - 2017
- [c48]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis. FPL 2017: 1-4 - [c47]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Pipelined Streaming Computation of Histogram in FPGA OpenCL. PARCO 2017: 632-641 - [c46]José L. Núñez-Yáñez, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia:
Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip. PARCO 2017: 677-686 - 2016
- [j26]José Luis Núñez-Yáñez, Mohammad Hosseinabady, Arash Beldachi:
Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling. IEEE Trans. Computers 65(5): 1484-1493 (2016) - 2015
- [c39]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Energy optimization of FPGA-based stream-oriented computing with power gating. FPL 2015: 1-6 - [c38]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices. FPL 2015: 1-6 - 2014
- [c33]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Run-time power gating in hybrid ARM-FPGA devices. FPL 2014: 1-6 - 2012
- [j16]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles. IET Comput. Digit. Tech. 6(1): 1-11 (2012) - [j15]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation. IET Comput. Digit. Tech. 6(6): 384-395 (2012) - [c25]José L. Núñez-Yáñez, Arash Beldachi, Atukem Nabina, Mohammad Hosseinabady:
Exploring dynamically reconfigurable multicore designs with NoRC designer. HPCS 2012: 254-260 - 2010
- [c24]Mohammad Hosseinabady, José L. Núñez-Yáñez:
SystemC Architectural Transaction Level Modelling for Large NoCs. FDL 2010: 142-147 - [c22]Mohammad Hosseinabady, José L. Núñez-Yáñez:
Effective modelling of large NoCs using SystemC. ISCAS 2010: 161-164 - [c21]Mohammad Hosseinabady, José Luis Núñez-Yáñez, Antonio Marcello Coppola:
Task Dispersal Measurement in Dynamic Reconfigurable NoCs. ISVLSI 2010: 167-172 - 2009
- [c20]José L. Núñez-Yáñez, Mohammad Hosseinabady, Atukem Nabina, Izhar Zaidi:
Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes. CCA/ISIC 2009: 308-313 - [c17]Mohammad Hosseinabady, José L. Núñez-Yáñez:
Run-time resource management in fault-tolerant network on reconfigurable chips. FPL 2009: 574-577 - 2008
- [c13]Mohammad Hosseinabady, José L. Núñez-Yáñez:
Fault-tolerant dynamically reconfigurable NoC-based SoC. ASAP 2008: 31-36
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