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Görschwin Fey

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Stefan Frehse

> Home > Persons > Görschwin Fey

Publications

2017
[j18]
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  dblp key:
  - journals/sttt/RienerHFSGDF17
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  - https://dblp.org/rec/journals/sttt/RienerHFSGDF17
Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey:
metaSMT: focus on your application and not on solver integration. Int. J. Softw. Tools Technol. Transf. 19(5): 605-621 (2017)
2013
[c79]
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  - conf/date/RienerFF13
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  - https://dblp.org/rec/conf/date/RienerFF13
Heinz Riener, Stefan Frehse, Görschwin Fey:
Improving fault tolerance utilizing hardware-software-co-synthesis. DATE 2013: 939-942
2012
[c69]
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  - electronic edition @ ieee.org
  - no references & citations available
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  dblp key:
  - conf/fmcad/FrehseFAYD12
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  - https://dblp.org/rec/conf/fmcad/FrehseFAYD12
Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav, Rolf Drechsler:
Complete and effective robustness checking by means of interpolation. FMCAD 2012: 82-90
2011
[j10]
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  - journals/tcad/FeySFD11
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  - https://dblp.org/rec/journals/tcad/FeySFD11
Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler:
Effective Robustness Analysis Using Bounded Model Checking Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1239-1252 (2011)
[c60]
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  - electronic edition @ ceur-ws.org (open access)
  - no references & citations available
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  dblp key:
  - conf/fmcad/HaedickeFFGD11
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  - https://dblp.org/rec/conf/fmcad/HaedickeFFGD11
Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler:
metaSMT: Focus on Your Application not on Solver Integration. DIFTS@FMCAD 2011
2010
[j8]
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  dblp key:
  - journals/it/FeySFD10
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  - https://dblp.org/rec/journals/it/FeySFD10
Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler:
Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits). it Inf. Technol. 52(4): 216-223 (2010)
[c55]
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  dblp key:
  - conf/ddecs/FrehseFD10
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  - https://dblp.org/rec/conf/ddecs/FrehseFD10
Stefan Frehse, Görschwin Fey, Rolf Drechsler:
A better-than-worst-case robustness measure. DDECS 2010: 78-83
[c54]
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  - conf/dsd/FrehseFSD10
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  - https://dblp.org/rec/conf/dsd/FrehseFSD10
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler:
RobuCheck: A Robustness Checker for Digital Circuits. DSD 2010: 226-231
[c53]
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  - conf/edcc/FrehseFSD10
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  - https://dblp.org/rec/conf/edcc/FrehseFSD10
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler:
RobuCheck: a robustness checker for digital circuits. DYADEM-FTS@EDCC 2010: 37-38
2009
[c45]
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  - conf/dsd/FrehseFSD09
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  - https://dblp.org/rec/conf/dsd/FrehseFSD09
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler:
Robustness Check for Multiple Faults Using Formal Techniques. DSD 2009: 85-90

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