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ORCIDAlex Ramírez
- > Home > Persons > Alex Ramírez
Publications
- 2012
[c69]Petar Radojkovic
, Paul M. Carpenter, Miquel Moretó, Alex Ramírez, Francisco J. Cazorla:
Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem. MICRO 2012: 401-412- 2011
- [j23]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Dynamic Cache Partitioning Based on the MLP of Cache Misses. Trans. High Perform. Embed. Archit. Compil. 3: 3-23 (2011) - 2009
- [j18]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Rizos Sakellariou, Mateo Valero:
FlexDCP: a QoS framework for CMP architectures. ACM SIGOPS Oper. Syst. Rev. 43(2): 86-96 (2009) - [c41]Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Thread to Core Assignment in SMT On-Chip Multiprocessors. SBAC-PAD 2009: 67-74 - 2008
- [j13]Kyle J. Nesbit, Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, James E. Smith:
Multicore Resource Management. IEEE Micro 28(3): 6-16 (2008) - [c40]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
MLP-Aware Dynamic Cache Partitioning. HiPEAC 2008: 337-352 - [c39]Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors. ICPP 2008: 173-181 - 2007
- [j12]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Explaining Dynamic Cache Partitioning Speed Ups. IEEE Comput. Archit. Lett. 6(1): 1-4 (2007) - [c36]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
MLP-Aware Dynamic Cache Partitioning. PACT 2007: 418 - [c32]Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero:
On the Problem of Minimizing Workload Execution Time in SMT Processors. ICSAMOS 2007: 66-73 - [c30]Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Online Prediction of Applications Cache Utility. ICSAMOS 2007: 169-177 - 2006
- [j9]Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Predictable Performance in SMT Processors: Synergy between the OS and SMTs. IEEE Trans. Computers 55(7): 785-799 (2006) - 2005
- [c27]Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Architectural support for real-time task scheduling in SMT processors. CASES 2005: 166-176 - 2004
- [j5]Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández:
Optimising long-latency-load-aware fetch policies for SMT processors. Int. J. High Perform. Comput. Netw. 2(1): 45-54 (2004) - [j4]Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández:
QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro 24(4): 24-31 (2004) - [c21]Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Predictable performance in SMT processors. Conf. Computing Frontiers 2004: 433-443 - [c20]Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Implicit vs. Explicit Resource Allocation in SMT Processors. DSD 2004: 44-51 - [c19]Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Feasibility of QoS for SMT. Euro-Par 2004: 535-540 - [c18]Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Enabling SMT for real-time embedded systems. EUSIPCO 2004: 1341-1344 - [c16]Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández:
DCache Warn: An I-Fetch Policy to Increase SMT Efficiency. IPDPS 2004 - [c14]Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández:
Dynamically Controlled Resource Allocation in SMT Processors. MICRO 2004: 171-182 - 2003
- [c13]Francisco J. Cazorla, Enrique Fernández, Alex Ramírez, Mateo Valero:
Improving Memory Latency Aware Fetch Policies for SMT Processors. ISHPC 2003: 70-85
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