Ginés Doménech-Asensi

◀ ▶ joint publications with Pablo Rubio-Ibáñez

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Publications

2021
[c26]
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Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi:
A library-based tool to translate high level DNN models into hierarchical VHDL descriptions. DCIS 2021: 1-5
2019
[c20]
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Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi:
Efficient VHDL Implementation of an Upscaling Function for Real Time Video Applications. ISCAS 2019: 1-5
2018
[j9]
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Pablo Rubio-Ibáñez, Ramón Ruiz Merino, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, José Ángel Díaz-Madrid, José-Alejandro López Alcantud:
An all-hardware implementation of the subpixel refinement stage in SIFT algorithm. Int. J. Circuit Theory Appl. 46(9): 1690-1702 (2018)
[c17]
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Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi:
FPGA real time synthesis of simplified SIFT algorithm. ICDSC 2018: 26:1-26:2

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