Kaisa Sere

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Juha Plosila

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Publications

2013
[j22]
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Sergey Ostroumov, Leonidas Tsiopoulos, Juha Plosila, Kaisa Sere:
Formal approach to agent-based dynamic reconfiguration in Networks-On-Chip. J. Syst. Archit. 59(9): 709-728 (2013)
[c54]
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Sergey Ostroumov, Leonidas Tsiopoulos, Kaisa Sere, Juha Plosila:
Generation of Structural VHDL Code with Library Components from Formal Event-B Models. DSD 2013: 111-118
2010
[j21]
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  - journals/ijertcs/TsiopoulosSP10
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Leonidas Tsiopoulos, Kaisa Sere, Juha Plosila:
Modeling Communication in Multi-Processor Systems-on-Chip Using Modular Connectors. Int. J. Embed. Real Time Commun. Syst. 1(2): 23-44 (2010)
2006
[c37]
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  - conf/pdcat/LiangPYS06
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Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere:
Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications. PDCAT 2006: 344-347
2005
[j19]
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  - journals/scp/PlosilaSW05
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Juha Plosila, Kaisa Sere, Marina Waldén:
Asynchronous system synthesis. Sci. Comput. Program. 55(1-3): 259-288 (2005)
[c35]
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Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere:
On-chip Debug for an Asynchronous Java Accelerator. PDCAT 2005: 312-315
2002
[c30]
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  - conf/fmco/PlosilaSW02
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Juha Plosila, Kaisa Sere, Marina Waldén:
Design with Asynchronously Communicating Components. FMCO 2002: 424-442
1997
[c19]
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  - conf/async/PlosilaS97
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Juha Plosila, Kaisa Sere:
Action Systems in Pipelined Processor Design. ASYNC 1997: 156-166

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