Paul Chow

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Gennady Feygin

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Publications

1996
[c12]
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David Yeh, Gennady Feygin, Paul Chow:
RACER: a reconfigurable constraint-length 14 Viterbi decoder. FCCM 1996: 60-69
1994
[j3]
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Gennady Feygin, P. Glenn Gulak, Paul Chow:
Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding. Inf. Process. Manag. 30(6): 805-816 (1994)
[c7]
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Gennady Feygin, P. Glenn Gulak, Paul Chow:
Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression. Data Compression Conference 1994: 254-263
1993
[j2]
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Gennady Feygin, Patrick Glenn Gulak, Paul Chow:
A multiprocessor architecture for Viterbi decoders with linear speedup. IEEE Trans. Signal Process. 41(9): 2907-2917 (1993)
[c5]
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Gennady Feygin, P. Glenn Gulak, Paul Chow:
Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding. Data Compression Conference 1993: 118-127
[c4]
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Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton:
A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. ISCAS 1993: 1945-1948
1991
[c3]
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Gennady Feygin, Patrick Glenn Gulak, Paul Chow:
Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up. ICASSP 1991: 1097-1100

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