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ORCIDPhilippe Olivier Alexandre Navaux
Publications
- 2022
[j54]Marcus Botacin, Francis B. Moreira, Philippe O. A. Navaux, André Grégio, Marco A. Z. Alves:
Terminator: A Secure Coprocessor to Accelerate Real-Time AntiViruses Using Inspection Breakpoints. ACM Trans. Priv. Secur. 25(2): 9:1-9:34 (2022)- 2019
- [c168]Emmanuell D. Carreño
, Marco A. Z. Alves, Matthias Diener, Eduardo Roloff, Philippe Olivier Alexandre Navaux:
Multi-phased Task Placement of HPC Applications in the Cloud. ISPDC 2019: 103-111 - 2017
- [j35]Matthias Diener, Eduardo H. M. Cruz, Marco A. Z. Alves, Philippe O. A. Navaux, Israel Koren:
Affinity-Based Thread and Data Mapping in Shared Memory Systems. ACM Comput. Surv. 49(4): 64:1-64:38 (2017) - [c144]Matthias Diener, Eduardo H. M. Cruz, Marco A. Z. Alves, Edson Borin, Philippe O. A. Navaux:
Optimizing memory affinity with a hybrid compiler/OS approach. Conf. Computing Frontiers 2017: 221-229 - 2016
- [j32]Francis B. Moreira, Marco A. Z. Alves, Matthias Diener, Philippe O. A. Navaux, Israel Koren:
A dynamic block-level execution profiler. Parallel Comput. 54: 15-28 (2016) - [j31]Eduardo Henrique Molina da Cruz, Matthias Diener, Marco A. Z. Alves, Laércio Lima Pilla, Philippe O. A. Navaux:
LAPT: A locality-aware page table for thread and data mapping. Parallel Comput. 54: 59-71 (2016) - [j27]Matthias Diener, Eduardo H. M. Cruz, Marco A. Z. Alves, Philippe O. A. Navaux, Anselm Busse, Hans-Ulrich Heiss:
Kernel-Based Thread and Data Mapping for Improved Memory Affinity. IEEE Trans. Parallel Distributed Syst. 27(9): 2653-2666 (2016) - [c118]Matthias Diener, Eduardo Henrique Molina da Cruz, Marco A. Z. Alves, Philippe O. A. Navaux:
Communication in Shared Memory: Concepts, Definitions, and Efficient Detection. PDP 2016: 151-158 - [c116]Paulo C. Santos, Marco A. Z. Alves, Matthias Diener, Luigi Carro, Philippe O. A. Navaux:
Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency. PDP 2016: 388-392 - 2015
- [c112]Matthias Diener, Eduardo Henrique Molina da Cruz, Marco A. Z. Alves, Mohammad S. Alhakeem, Philippe Olivier Alexandre Navaux, Hans-Ulrich Heiß:
Locality and Balance for Communication-Aware Thread Mapping in Multicore Systems. Euro-Par 2015: 196-208 - [c110]Marco A. Z. Alves, Carlos Villavieja, Matthias Diener, Francis Birck Moreira, Philippe Olivier Alexandre Navaux:
SiNUCA: A Validated Micro-Architecture Simulator. HPCC/CSS/ICESS 2015: 605-610 - 2014
- [j20]Eduardo Henrique Molina da Cruz, Matthias Diener, Marco A. Z. Alves, Philippe Olivier Alexandre Navaux:
Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols. J. Parallel Distributed Comput. 74(3): 2215-2228 (2014) - [c92]Eduardo Henrique Molina da Cruz, Matthias Diener, Marco A. Z. Alves, Laércio Lima Pilla, Philippe Olivier Alexandre Navaux:
Optimizing Memory Locality Using a Locality-Aware Page Table. SBAC-PAD 2014: 198-205 - 2013
- [c88]Marco A. Z. Alves, Carlos Villavieja, Matthias Diener, Philippe Olivier Alexandre Navaux:
Energy Efficient Last Level Caches via Last Read/Write Prediction. SBAC-PAD 2013: 73-80 - 2012
- [j15]Eduardo Henrique Molina da Cruz, Marco Antonio Zanata Alves, Alexandre Carissimi, Philippe Olivier Alexandre Navaux, Christiane Pousa Ribeiro, Jean-François Méhaut:
Memory-aware Thread and Data Mapping for Hierarchical Multi-core Platforms. Int. J. Netw. Comput. 2(1): 97-116 (2012) - [c80]Marco A. Z. Alves, Khubaib, Eiman Ebrahimi, Veynu Narasiman, Carlos Villavieja, Philippe Olivier Alexandre Navaux, Yale N. Patt:
Energy Savings via Dead Sub-Block Prediction. SBAC-PAD 2012: 51-58 - 2011
- [j11]Mateus B. Rutzig, Antonio Carlos Schneider Beck, Felipe Lopes Madruga, Marco A. Z. Alves, Henrique C. Freitas, Nicolas Maillard, Philippe Olivier Alexandre Navaux, Luigi Carro:
Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment. Int. J. Reconfigurable Comput. 2011: 546962:1-546962:13 (2011) - [j10]Marco A. Z. Alves, Henrique C. Freitas, Philippe Olivier Alexandre Navaux:
High Latency and Contention on Shared L2-Cache for Many-Core Architectures. Parallel Process. Lett. 21(1): 85-106 (2011) - [c78]Eduardo Henrique Molina da Cruz, Marco Antonio Zanata Alves, Alexandre Carissimi, Philippe Olivier Alexandre Navaux, Christiane Pousa Ribeiro, Jean-François Méhaut:
Using Memory Access Traces to Map Threads and Data on Hierarchical Multi-core Platforms. IPDPS Workshops 2011: 551-558 - 2010
- [c74]Matthias Diener, Felipe Lopes Madruga, Eduardo Rocha Rodrigues, Marco A. Z. Alves, Jörg Schneider, Philippe Olivier Alexandre Navaux, Hans-Ulrich Heiss:
Evaluating Thread Placement Based on Memory Access Patterns for Multi-core Processors. HPCC 2010: 491-496 - [c72]Mateus B. Rutzig, Felipe Lopes Madruga, Marco A. Z. Alves, Henrique Cota de Freitas, Antonio Carlos Schneider Beck, Nicolas Maillard, Philippe Olivier Alexandre Navaux, Luigi Carro:
TLP and ILP exploitation through a reconfigurable multiprocessor system. IPDPS Workshops 2010: 1-8 - [c69]Henrique Cota de Freitas, Lucas Mello Schnorr, Marco Antonio Zanata Alves, Philippe Olivier Alexandre Navaux:
Impact of Parallel Workloads on NoC Architecture Design. PDP 2010: 551-555 - 2009
- [c58]Henrique C. Freitas, Felipe Lopes Madruga, Marco A. Z. Alves, Philippe Olivier Alexandre Navaux:
Design of Interleaved Multithreading for Network Processors on Chip. ISCAS 2009: 2213-2216 - [c55]Henrique C. Freitas, Marco A. Z. Alves, Lucas Mello Schnorr, Philippe Olivier Alexandre Navaux:
Performance Evaluation of NoC Architectures for Parallel Workloads. NOCS 2009: 87
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