Rubin A. Parekhji

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Arvind Jain

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Publications

2015
[j8]
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Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji:
Time-Division Multiplexing for Testing DVFS-Based SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 668-681 (2015)
2014
[c44]
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Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain:
Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing. DATE 2014: 1-6
2012
[j7]
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Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji:
Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(11): 1754-1766 (2012)
[c41]
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Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji:
Time-division multiplexing for testing SoCs with DVS and multiple voltage islands. ETS 2012: 1-6
2011
[j6]
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Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi:
Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test. J. Low Power Electron. 7(4): 502-515 (2011)
[c39]
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Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji:
Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands. Asian Test Symposium 2011: 33-39
[c36]
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  - conf/vlsid/JainSPR11
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Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi:
Multi-CoDec Configurations for Low Power and High Quality Scan Test. VLSI Design 2011: 370-375

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