Chun Zhang

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Xuan Ma

> Home > Persons > Chun Zhang

Publications

2013
[c88]
- view
  authority control:
- export record
  dblp key:
  - conf/vlsi-dat/YuZHXWZW13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsi-dat/YuZHXWZW13
Kunzhi Yu, Xuqiang Zheng, Ke Huang, Xuan Ma, Ziqiang Wang, Chun Zhang, Zhihua Wang:
A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS. VLSI-DAT 2013: 1-4
2012
[c72]
- view
  authority control:
- export record
  dblp key:
  - conf/mwscas/HuangWZMYZW12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/mwscas/HuangWZMYZW12
Ke Huang, Ziqiang Wang, Xuqiang Zheng, Xuan Ma, Kunzhi Yu, Chun Zhang, Zhihua Wang:
A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS. MWSCAS 2012: 932-935
[c71]
- view
  authority control:
- export record
  dblp key:
  - conf/mwscas/YuWMZZW12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/mwscas/YuWMZZW12
Kunzhi Yu, Ziqiang Wang, Xuan Ma, Xuqiang Zheng, Chun Zhang, Zhihua Wang:
A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS. MWSCAS 2012: 936-939

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.