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ORCIDShin'ichi Wakabayashi
- > Home > Persons > Shin'ichi Wakabayashi
Publications
- 2002
[j8]Shinya Yamasaki, Shingo Nakaya, Shin'ichi Wakabayashi, Tetsushi Koide:
A Performance-Driven Floorplanning Method with Interconnect Performance Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2775-2784 (2002)- [j7]Shigeki Takekawa, Shin'ichi Wakabayashi, Tetsushi Koide:
A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time. Syst. Comput. Jpn. 33(12): 87-96 (2002) - 2001
- [j6]Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide:
Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual. Syst. Comput. Jpn. 32(1): 29-37 (2001) - 2000
- [c20]Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Masataka Yamane, Hajime Ueno:
Genetic algorithm accelerator GAA-II. ASP-DAC 2000: 9-10 - [c19]Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi:
Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. ASP-DAC 2000: 99-104 - [c18]Shingo Nakaya, Tetsushi Koide, Shin'ichi Wakabayashi:
An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair. ISCAS 2000: 65-68 - 1999
- [j5]Tetsushi Koide, Shin'ichi Wakabayashi:
A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. Integr. 27(1): 57-76 (1999) - [c17]Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta:
An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. ASP-DAC 1999: 37-40 - [c16]Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide:
Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. ASP-DAC 1999: 181-184 - 1998
- [c15]Tetsushi Koide, Shin'ichi Wakabayashi:
A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. ASP-DAC 1998: 577-583 - [c14]Koichi Hatta, Masashige Suzuki, Shin'ichi Wakabayashi, Tetsushi Koide:
Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. PPSN 1998: 1028-1037 - 1997
- [j4]Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida:
A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. Integr. 24(1): 53-77 (1997) - [c13]Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru:
Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs. ASP-DAC 1997: 133-140 - 1996
- [j3]Tetsushi Koide, Masahiro Tsuchiya, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
A three-layer over-the-cell multi-channel router for a new cell model. Integr. 21(3): 171-189 (1996) - [j2]Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
Pin assignment with global routing for VLSI building block layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1575-1583 (1996) - 1995
- [c12]Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
A new system partitioning method under performance and physical constraints for multi-chip modules. ASP-DAC 1995 - [c11]Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru:
A new performance driven placement method with the Elmore delay model for row based VLSIs. ASP-DAC 1995 - [c10]Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
A three-layer over-cell multi-channel routing method for a new cell model. ASP-DAC 1995 - [c9]Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida:
An MCM Routing Algorithm Considering Crosstalk. ISCAS 1995: 211-214 - [c8]Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida:
A Verification Algorithm for Logic Circuits with Internal Variables. ISCAS 1995: 1920-1923 - 1994
- [c7]Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
A Floorplanning Method with Topological Constraint Manipulation. ISCAS 1994: 165-168 - [c5]Shin'ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida:
A Systolic Graph Partitioning Algorithm for VLSI Design. ISCAS 1994: 225-228 - 1993
- [c4]Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
A new global routing algorithm for over-the-cell routing in standard cell layouts. EURO-DAC 1993: 116-121 - [c3]Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida:
Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. ISCAS 1993: 2059-2062 - 1992
- [c2]Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
An optimal channel pin assignment with multiple intervals for building block layout. EURO-DAC 1992: 348-353
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