Takayuki Watanabe

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Atsushi Kamo

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Publications

2005
[c19]
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Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits. ISCAS (5) 2005: 4903-4906
2004
[c17]
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Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits. DATE 2004: 1327-1333
2002
[j1]
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  - electronic edition @ ieice.org
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Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
An Efficient Simulator for Multiport Interconnects with Model Order Reduction Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(6): 1214-1219 (2002)
[c11]
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I. Hattori, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method. ISCAS (5) 2002: 29-32
[c10]
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Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique. ISCAS (5) 2002: 649-552
2001
[c6]
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  - conf/iscas/SuzukiMKWA01
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Masaya Suzuki, Hirofumi Miyashita, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
High-speed interconnect simulation using MIMO type of adaptive least square method. ISCAS (5) 2001: 327-330
[c5]
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Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Simulation for the optimal placement of decoupling capacitors on printed circuit board. ISCAS (3) 2001: 727-730
1999
[c4]
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Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Expanded GMC for transient analysis of transmission line networks. ISCAS (6) 1999: 33-36

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