Nicola Nicolici

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Ho Fai Ko

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Publications

2013
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Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici:
Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation. DAC 2013: 121:1-121:6
2012
[j41]
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Ho Fai Ko, Nicola Nicolici:
Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging. IEEE Trans. Computers 61(11): 1563-1575 (2012)
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Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici:
In-system constrained-random stimuli generation for post-silicon validation. ITC 2012: 1-10
2011
[j29]
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  - journals/tvlsi/KoKN11
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Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici:
Design-for-Debug Architecture for Distributed Embedded Logic Analysis. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1380-1393 (2011)
2010
[c51]
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Ho Fai Ko, Nicola Nicolici:
Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging. ETS 2010: 62-67
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Ho Fai Ko, Nicola Nicolici:
Automated trace signals selection using the RTL descriptions. ITC 2010: 144-153
2009
[j25]
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  - journals/tcad/KoN09
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Ho Fai Ko, Nicola Nicolici:
Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 285-297 (2009)
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Ho Fai Ko, Nicola Nicolici:
Resource-Efficient Programmable Trigger Units for Post-Silicon Validation. ETS 2009: 17-22
[c41]
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Nicola Nicolici, Ho Fai Ko:
Design-for-debug for post-silicon validation: Can high-level descriptions help? HLDVT 2009: 172-175
2008
[j21]
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Ho Fai Ko, Nicola Nicolici:
Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy. J. Electron. Test. 24(4): 393-403 (2008)
[j20]
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Ho Fai Ko, Nicola Nicolici:
Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 2092-2097 (2008)
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Ho Fai Ko, Nicola Nicolici:
On Automated Trigger Event Generation in Post-Silicon Validation. DATE 2008: 256-259
[c37]
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Ho Fai Ko, Nicola Nicolici:
Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation. DATE 2008: 1298-1303
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Ho Fai Ko, Nicola Nicolici:
A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test. ISQED 2008: 649-654
[c32]
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Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici:
Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs. ITC 2008: 1-10
2006
[c28]
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  - conf/iccd/KoN06
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Ho Fai Ko, Nicola Nicolici:
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. ICCD 2006: 237-242
2005
[c27]
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  - conf/aspdac/KoXN05
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Ho Fai Ko, Qiang Xu, Nicola Nicolici:
Register-transfer level functional scan for hierarchical designs. ASP-DAC 2005: 1172-1175
2004
[c22]
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  - conf/ats/KoN04
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Ho Fai Ko, Nicola Nicolici:
Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing. Asian Test Symposium 2004: 454-459
[c20]
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Ho Fai Ko, Nicola Nicolici:
Functional Illinois Scan Design at RTL. ICCD 2004: 78-81

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