Toshiyuki Okayasu

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▷ joint publications with Kazuhiro Yamamoto

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Publications

2009
[c8]
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Tasuku Fujibe, Masakatsu Suda, Kazuhiro Yamamoto, Yoshihito Nagata, Kazuhiro Fujita, Daisuke Watanabe, Toshiyuki Okayasu:
Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing. ITC 2009: 1-10
2007
[c7]
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  - conf/cicc/YamamotoSO07
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Kazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu:
2GS/s, 10ps Resolution CMOS Differential Time-to-Digital Converter for Real-Time Testing of Source-Synchronous Memory Device. CICC 2007: 145-148
2006
[c6]
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  - conf/isscc/OkayasuSYKSW06
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Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto, Shusuke Kantake, Satoshi Sudou, Daisuke Watanabe:
1.83ps-Resolution CMOS Dynamic Arbitrary Timing Generator for >4GHz ATE Applications. ISSCC 2006: 2122-2131
[c5]
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  - conf/itc/YamamotoSONT06
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Kazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu, Hirokatsu Niijima, Koichi Tanaka:
Multi Strobe Circuit for 2.133GHz Memory Test System. ITC 2006: 1-9
2005
[c4]
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  - conf/itc/SudaYOKSW05
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Masakatsu Suda, Kazuhiro Yamamoto, Toshiyuki Okayasu, Shusuke Kantake, Satoshi Sudou, Daisuke Watanabe:
CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test system. ITC 2005: 9
2002
[c2]
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  - conf/itc/OkayasuSY02
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Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto:
CMOS Circuit Technology for Precise GHz Timing Generator. ITC 2002: 894-902

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