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Eric Martin 0001
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Publications
- 2012
- [c52]Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin:
A design approach dedicated to network-based and conflict-free parallel interleavers. ACM Great Lakes Symposium on VLSI 2012: 153-158 - 2011
- [c51]Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin:
A methodology based on Transportation problem modeling for designing parallel interleaver architectures. ICASSP 2011: 1613-1616 - [c50]Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin:
An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture. ISCAS 2011: 1720-1723 - 2010
- [c49]Ghizlane Lhairech-Lebreton, Philippe Coussy, Eric Martin:
Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA. FPL 2010: 464-468 - [c48]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
Static Address Generation Easing: a design methodology for parallel interleaver architectures. ICASSP 2010: 1594-1597 - [c47]Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin:
Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach. ICECS 2010: 466-469 - [c46]Ghizlane Lhairech-Lebreton, Philippe Coussy, Dominique Heller, Eric Martin:
Bitwidth-aware high-level synthesis for designing low-power DSP applications. ICECS 2010: 531-534 - [i11]Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard:
Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures. CoRR abs/1002.3990 (2010) - 2009
- [j12]Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin:
Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis. J. Signal Process. Syst. 56(2-3): 167-186 (2009) - 2007
- [j10]Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin:
Constrained algorithmic IP design for system-on-chip. Integr. 40(2): 94-105 (2007) - [c45]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
Application of a design space exploration tool to enhance interleaver generation. EUSIPCO 2007: 846-850 - [c44]Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin:
Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system. EUSIPCO 2007: 1625-1629 - [c43]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
A design methodology for space-time adapter. ACM Great Lakes Symposium on VLSI 2007: 347-352 - [c42]Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin:
A design flow dedicated to multi-mode architectures for DSP applications. ICCAD 2007: 604-611 - [c41]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. ISCAS 2007: 2946-2949 - [i10]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. CoRR abs/0706.1692 (2007) - [i9]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
A Design Methodology for Space-Time Adapter. CoRR abs/0706.2732 (2007) - [i8]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels. CoRR abs/0706.2824 (2007) - [i7]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
Application of a design space exploration tool to enhance interleaver generation. CoRR abs/0706.3009 (2007) - 2006
- [j8]Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin:
A formal method for hardware IP design and integration under I/O and timing constraints. ACM Trans. Embed. Comput. Syst. 5(1): 29-53 (2006) - [c40]Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin:
Design Space Exploration of DSP Applications Based on Behavioral Description Models. SiPS 2006: 244-249 - [i4]Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin:
High-level synthesis under I/O Timing and Memory constraints. CoRR abs/cs/0605143 (2006) - [i1]Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin:
Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI. CoRR abs/cs/0605146 (2006) - 2005
- [c35]Lobna Kriaa, S. Adriano, Emmanuel Vaumorin, R. Nouacer, F. Blanc, S. Pajaniardja, Philippe Coussy, Eric Martin, Dominique Heller, Farhat Thabet, Anne-Marie Fouilliart:
SystemCmantic: A high level Modelling and Co-Design Framework. FDL 2005: 341-353 - [c34]Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin:
A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example]. ICASSP (5) 2005: 61-64 - [c33]Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin:
High-level synthesis under I/O timing and memory constraints. ISCAS (1) 2005: 680-683 - 2004
- [c24]Philippe Coussy, David Gnaedig, Amor Nafkha, Adel Baganne, Emmanuel Boutillon, Eric Martin:
A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder. ICASSP (5) 2004: 45-48 - 2003
- [c17]Philippe Coussy, Adel Baganne, Eric Martin:
Communication and Timing Constraints Analysis for IP Design and Integration. VLSI-SOC 2003: 38-43 - 2002
- [c16]Philippe Coussy, Adel Baganne, Eric Martin:
A design methodology for integrating IP into SOC systems. CICC 2002: 307-310 - [c15]Philippe Coussy, Adel Baganne, Eric Martin:
IP cores integration in DSP System-on-chip designs. EUSIPCO 2002: 1-4 - [c13]Philippe Coussy, Adel Baganne, Eric Martin:
Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder. ICECS 2002: 733-736 - [c12]Philippe Coussy, Adel Baganne, Eric Martin:
A design methodology for IP integration. ISCAS (4) 2002: 711-714
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