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Tomokazu Yoneda
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Publications
- 2017
- [j18]Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue:
An Effective and Sensitive Scan Segmentation Technique for Detecting Hardware Trojan. IEICE Trans. Inf. Syst. 100-D(1): 130-139 (2017) - [j17]Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass, Chia Yee Ooi, Tomokazu Yoneda, Michiko Inoue:
An integrated DFT solution for power reduction in scan test applications by low power gating scan cell. Integr. 57: 108-124 (2017) - [c38]Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue, Alex Orailoglu:
Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection. ATS 2017: 52-57 - [c37]Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue, Alex Orailoglu:
Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions. ETS 2017: 1-6 - 2016
- [j16]Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue:
Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair. IEICE Trans. Inf. Syst. 99-D(10): 2591-2599 (2016) - [c36]Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue:
Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC. ETS 2016: 1-2 - 2015
- [c35]Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato:
An ECC-based memory architecture with online self-repair capabilities for reliability enhancement. ETS 2015: 1-6 - 2014
- [c34]Yussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue:
Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units. ATS 2014: 292-297 - [c33]Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue:
Memory block based scan-BIST architecture for application-dependent FPGA testing. FPGA 2014: 85-88 - 2012
- [j15]Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hideo Fujiwara:
Test Pattern Ordering and Selection for High Quality Test Set under Constraints. IEICE Trans. Inf. Syst. 95-D(12): 3001-3009 (2012) - [j14]Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara:
A Failure Prediction Strategy for Transistor Aging. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1951-1959 (2012) - [c32]Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura:
DART: Dependable VLSI test architecture and its implementation. ITC 2012: 1-10 - [c31]Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue:
A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation. ITC 2012: 1-8 - 2011
- [j13]Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara:
Balanced Secure Scan: Partial Scan Approach for Secret Information Protection. J. Electron. Test. 27(2): 99-108 (2011) - [c30]Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara:
Temperature-Variation-Aware Test Pattern Optimization. ETS 2011: 214 - [c29]Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara:
Faster-than-at-speed test for increased test quality and in-field reliability. ITC 2011: 1-9 - 2010
- [c27]Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara:
Seed Ordering and Selection for High Quality Delay Test. Asian Test Symposium 2010: 313-318 - [c26]Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara:
Test pattern selection to optimize delay test quality with a limited size of test set. ETS 2010: 260 - [c25]Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara:
Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS 2010: 21-26 - [c24]Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara:
Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. VTS 2010: 188-193 - 2009
- [c22]Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara:
Partial Scan Approach for Secret Information Protection. ETS 2009: 143-148
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