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ORCIDTakashi Nanya
- > Home > Persons > Takashi Nanya
Publications
- 2010
[c62]Masashi Imai, Tomohide Nagai, Takashi Nanya:
Pair and swap: An approach to graceful degradation for dependable chip multiprocessors. DSN Workshops 2010: 119-124- [c59]James L. Weston, Masashi Imai, Tomohide Nagai, Takashi Nanya:
An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors. PRDC 2010: 62-69 - 2009
- [c58]Masashi Imai, Kouei Takada, Takashi Nanya:
Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors. ASYNC 2009: 209-216 - [c57]Masashi Imai, Tomohiro Yoneda, Takashi Nanya:
N-way ring and square arbiters. ICCD 2009: 125-130 - 2008
- [c55]Masashi Imai, Takashi Nanya:
A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries. ACSD 2008: 21-26 - 2007
- [c48]Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura
, Takashi Nanya:
Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. DATE 2007: 797-802 - 2006
- [j25]Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya:
Design Method of High Performance and Low Power Functional Units Considering Delay Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3519-3528 (2006) - [c40]Masashi Imai, Takashi Nanya:
A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. ASYNC 2006: 68-77 - 2004
- [c35]Masashi Imai, Metehan Özcan, Takashi Nanya:
Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. ASYNC 2004: 62-71 - [c34]Masayuki Tsukisaka, Masashi Imai, Takashi Nanya:
Asynchronous Scan-Latch controller for Low Area Overhead DFT. ICCD 2004: 66-71 - [c33]Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya:
Skewed Checkpointing for Tolerating Multi-Node Failures. SRDS 2004: 116-125 - 2003
- [j23]Nattha Sretasereekul, Hiroshi Saito, Euiseok Kim, Metehan Özcan, Masashi Imai, Hiroshi Nakamura, Takashi Nanya:
Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3028-3037 (2003) - [c30]Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya:
Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. ASYNC 2003: 184-195 - [c27]Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya:
A zero-time-overhead asynchronous four-phase controller. ISCAS (5) 2003: 205-208 - [c26]Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya:
Control signal sharing of asynchronous circuits using datapath delay information. ISCAS (5) 2003: 617-620 - 2002
- [c25]Metehan Özcan, Masashi Imai, Takashi Nanya:
Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits. ASYNC 2002: 109-114 - [c22]Masayuki Tsukisaka, Masashi Imai, Takashi Nanya:
High Throughput Asynchronous Domino Using Dual output Buffer. IWLS 2002: 279-282 - 2001
- [c18]Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno:
Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. ASYNC 2001: 162-172 - 1998
- [c15]Akihiro Takamura, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Yoichiro Ueno, Masashi Imai, Masashi Kuwako, Takashi Nanya:
TITAC-2: An Asynchronous 32-bit Microprocessor. ASP-DAC 1998: 319-320 - 1997
- [c13]Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya:
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. ICCD 1997: 288-294
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