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Swaroop Ghosh
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Publications
- 2015
- [j17]Swaroop Ghosh, Abhishek Basak, Swarup Bhunia:
How Secure Are Printed Circuit Boards Against Trojan Attacks? IEEE Des. Test 32(2): 7-16 (2015) - [j14]Robert Karam, Ruchir Puri, Swaroop Ghosh, Swarup Bhunia:
Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories. Proc. IEEE 103(8): 1311-1330 (2015) - [c35]Jae-Won Jang, Jongsun Park, Swaroop Ghosh, Swarup Bhunia:
Self-correcting STTRAM under magnetic field attacks. DAC 2015: 77:1-77:6 - 2010
- [j8]Patrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 53-65 (2010) - 2007
- [j5]Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 1947-1956 (2007) - [j4]Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
Low-Power and testable circuit synthesis using Shannon decomposition. ACM Trans. Design Autom. Electr. Syst. 12(4): 47 (2007) - [c11]Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling. DATE 2007: 1532-1537 - [c10]Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy:
Tolerance to Small Delay Defects by Adaptive Clock Stretching. IOLTS 2007: 244-252 - 2006
- [j3]Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy:
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2934-2943 (2006) - [c7]Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. ICCAD 2006: 619-624 - [c6]Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy:
Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. IOLTS 2006: 31-36 - 2005
- [c4]Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. Asian Test Symposium 2005: 404-409 - [c3]Arijit Raychowdhury, Swaroop Ghosh, Swarup Bhunia, Debjyoti Ghosh, Kaushik Roy:
A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points. ETS 2005: 108-113
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