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Robert K. Montoye
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Publications
- 2014
- [j10]Jing Li, Robert K. Montoye, Masatoshi Ishii, Leland Chang:
1 Mb 0.41 µm2 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing. IEEE J. Solid State Circuits 49(4): 896-907 (2014) - 2013
- [c17]Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert K. Montoye, Leland Chang, José A. Tierno, Daniel J. Friedman:
A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. ISSCC 2013: 400-401 - 2011
- [c15]Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran, José A. Tierno, Leland Chang, Dharmendra S. Modha, Daniel J. Friedman:
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. CICC 2011: 1-4 - [c14]Gary S. Ditlow, Robert K. Montoye, Salvatore N. Storino, Sherman M. Dance, Sebastian Ehrenreich, Bruce M. Fleischer, Thomas W. Fox, Kyle M. Holmes, Junichi Mihara, Yutaka Nakamura, Shohji Onishi, Robert Shearer, Dieter F. Wendel, Leland Chang:
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. ISSCC 2011: 256-258 - 2010
- [j9]Leland Chang, David J. Frank, Robert K. Montoye, Steven J. Koester, Brian L. Ji, Paul W. Coteus, Robert H. Dennard, Wilfried Haensch:
Practical Strategies for Power-Efficient Computing Technologies. Proc. IEEE 98(2): 215-236 (2010) - 2008
- [j7]Leland Chang, Robert K. Montoye, Yutaka Nakamura, Kevin Batson, Richard J. Eickemeyer, Robert H. Dennard, Wilfried Haensch, Damir Jamsek:
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches. IEEE J. Solid State Circuits 43(4): 956-963 (2008)
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