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Dhamin Al-Khalili

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Shuli Gao

> Home > Persons > Dhamin Al-Khalili

Publications

2017
[j25]
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  - journals/ijrc/GaoALC17
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  - https://dblp.org/rec/journals/ijrc/GaoALC17
Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini:
Efficient Realization of BCD Multipliers Using FPGAs. Int. J. Reconfigurable Comput. 2017: 2410408:1-2410408:12 (2017)
[c39]
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  - conf/ccece/GaoALC17
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  - https://dblp.org/rec/conf/ccece/GaoALC17
Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini:
Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier. CCECE 2017: 1-6
2012
[j23]
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  - journals/iet-cdt/GaoACL12
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  - https://dblp.org/rec/journals/iet-cdt/GaoACL12
Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois:
Asymmetric large size multipliers with optimised FPGA resource utilisation. IET Comput. Digit. Tech. 6(6): 372-383 (2012)
[c37]
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  - conf/newcas/GaoAC12
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Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
An improved BCD adder using 6-LUT FPGAs. NEWCAS 2012: 13-16
2011
[c35]
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  - conf/icecsys/GaoAC11
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Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs. ICECS 2011: 137-140
[c32]
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  - conf/ipps/GaoAC11
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Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs. IPDPS Workshops 2011: 271-277
2010
[j22]
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  - journals/vlsisp/GaoCAL10
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Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers. J. Signal Process. Syst. 58(1): 3-15 (2010)
2009
[j21]
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  - journals/ijrc/GaoAC09
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Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs. Int. J. Reconfigurable Comput. 2009: 145130:1-145130:11 (2009)
[c30]
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  - conf/icecsys/GaoAC09
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Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
Two level decomposition based matrix multiplication for FPGAs. ICECS 2009: 427-430
2007
[j19]
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  - journals/iet-cdt/GaoCAL07
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Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
Optimised realisations of large integer multipliers and squarers using embedded blocks. IET Comput. Digit. Tech. 1(1): 9-16 (2007)
[c28]
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  - conf/asap/GaoCAL07
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Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. ASAP 2007: 18-23
2006
[c27]
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  - conf/aiccsa/GaoCAL06
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Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers. AICCSA 2006: 248-254
[c25]
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  - conf/socc/GaoACL06
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Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois:
Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers. SoCC 2006: 21-24

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