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Greg Stitt

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with James Coole

> Home > Persons > Greg Stitt

Publications

2018
[c49]
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  dblp key:
  - conf/heart/0004SC18
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  persistent URL:
  - https://dblp.org/rec/conf/heart/0004SC18
David Wilson, Greg Stitt, James Coole:
A Recurrently Generated Overlay Architecture for Rapid FPGA Application Development. HEART 2018: 4:1-4:6
2015
[c41]
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  dblp key:
  - conf/fccm/CooleS15
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  - https://dblp.org/rec/conf/fccm/CooleS15
James Coole, Greg Stitt:
Adjustable-Cost Overlays for Runtime Compilation. FCCM 2015: 21-24
2014
[j22]
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  - journals/micro/CooleS14
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  - https://dblp.org/rec/journals/micro/CooleS14
James Coole, Greg Stitt:
Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts. IEEE Micro 34(1): 42-53 (2014)
2012
[c31]
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  - conf/codes/CooleS12
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James Coole, Greg Stitt:
BPR: fast FPGA placement and routing using macroblocks. CODES+ISSS 2012: 275-284
2011
[j15]
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  - journals/dt/StittGLSAWRHKC11
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Greg Stitt, Alan D. George, Herman Lam, Melissa C. Smith, Vikas Aggarwal, Gongyu Wang, Casey Reardon, Brian Holland, Seth Koehler, James Coole:
An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing. IEEE Des. Test Comput. 28(4): 68-77 (2011)
[j14]
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  - journals/esl/StittC11
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Greg Stitt, James Coole:
Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation. IEEE Embed. Syst. Lett. 3(3): 81-84 (2011)
2010
[j9]
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  - journals/ijrc/CooleS10
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James Coole, Greg Stitt:
Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures. Int. J. Reconfigurable Comput. 2010: 652620:1-652620:16 (2010)
[c26]
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  - conf/codes/CooleS10
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James Coole, Greg Stitt:
Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing. CODES+ISSS 2010: 13-22
2009
[c19]
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  - conf/reconfig/CooleWS09
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James Coole, John Robert Wernsing, Greg Stitt:
A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation. ReConFig 2009: 143-148
2008
[c15]
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  - conf/codes/StittCC08
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Greg Stitt, Gaurav Chaudhari, James Coole:
Traversal caches: a first step towards FPGA acceleration of pointer-based data structures. CODES+ISSS 2008: 61-66

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