N. Pete Sedcole

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▷ joint publications with Justin S. J. Wong

> Home > Persons > N. Pete Sedcole

Publications

2010
[c24]
- view
  authority control:
- export record
  dblp key:
  - conf/fpga/StottWSC10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpga/StottWSC10
Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung:
Degradation in FPGAs: measurement and modelling. FPGA 2010: 229-238
2009
[j3]
- view
  authority control:
- export record
  dblp key:
  - journals/trets/WongSC09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/trets/WongSC09
Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung:
Self-Measurement of Combinatorial Circuit Delays in FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 10:1-10:22 (2009)
2008
[c20]
- view
  authority control:
- export record
  dblp key:
  - conf/fpga/SedcoleWC08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpga/SedcoleWC08
N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung:
Measuring and modeling FPGA clock variability. FPGA 2008: 258
[c18]
- view
  authority control:
- export record
  dblp key:
  - conf/fpl/WongCS08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpl/WongCS08
Justin S. J. Wong, Peter Y. K. Cheung, N. Pete Sedcole:
Combating process variation on FPGAS with a precise at-speed delay measurement method. FPL 2008: 703-704
[c16]
- view
  authority control:
- export record
  dblp key:
  - conf/fpt/WongSC08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpt/WongSC08
Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung:
A transition probability based delay measurement method for arbitrary circuits on FPGAs. FPT 2008: 105-112
[c15]
- view
  authority control:
- export record
  dblp key:
  - conf/fpt/SedcoleWC08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpt/SedcoleWC08
N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung:
Modelling and compensating for clock skew variability in FPGAs. FPT 2008: 217-224
[c14]
- view
  authority control:
- export record
  dblp key:
  - conf/isvlsi/SedcoleWC08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isvlsi/SedcoleWC08
N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung:
Characterisation of FPGA Clock Variability. ISVLSI 2008: 322-328
2007
[c9]
- view
  authority control:
- export record
  dblp key:
  - conf/fpt/WongSC07
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpt/WongSC07
Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung:
Self-characterization of Combinatorial Circuit Delays in FPGAs. FPT 2007: 17-23

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.