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Cheng-Kok Koh
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Publications
- 2007
- [j19]Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden:
Routability-Driven Placement and White Space Allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 858-871 (2007) - 2004
- [c44]Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden:
Routability-driven placement and white space allocation. ICCAD 2004: 394-401 - 2001
- [j5]Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan:
Interconnect sizing and spacing with consideration of couplingcapacitance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9): 1164-1169 (2001) - [j4]Jason Cong, Cheng-Kok Koh, Patrick H. Madden:
Interconnect layout optimization under higher order RLC model forMCM designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(12): 1455-1463 (2001) - 1998
- [j3]Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing. ACM Trans. Design Autom. Electr. Syst. 3(3): 341-388 (1998) - 1997
- [c7]Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo:
Interconnect design for deep submicron ICs. ICCAD 1997: 478-485 - [c6]Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan:
Global interconnect sizing and spacing with consideration of coupling capacitance. ICCAD 1997: 628-633 - [c5]Jason Cong, Cheng-Kok Koh:
Interconnect layout optimization under higher-order RLC model. ICCAD 1997: 713-720 - 1996
- [j2]Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden:
Performance optimization of VLSI interconnect layout. Integr. 21(1-2): 1-94 (1996) - [c4]Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung:
Simultaneous buffer and wire sizing for performance and power optimization. ISLPED 1996: 271-276 - 1995
- [c3]Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing under Elmore delay. ICCAD 1995: 66-71 - [c2]Jason Cong, Cheng-Kok Koh:
Minimum-Cost Bounded-Skew Clock Routing. ISCAS 1995: 215-218 - 1994
- [j1]Jason Cong, Cheng-Kok Koh:
Simultaneous driver and wire sizing for performance and power optimization. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 408-425 (1994) - [c1]Jason Cong, Cheng-Kok Koh:
Simultaneous driver and wire sizing for performance and power optimization. ICCAD 1994: 206-212
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