Yongpan Liu

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Hongyang Jia

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Publications

2024
[c142]
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Yifan He, Shupei Fan, Xuan Li, Luchang Lei, Wenbin Jia, Chen Tang, Yaolei Li, Zongle Huang, Zhike Du, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu:
34.7 A 28nm 2.4Mb/mm² 6.9 - 16.3TOPS/mm² eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing. ISSCC 2024: 578-580
2023
[j72]
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Yifan He, Jinshan Yue, Xiaoyu Feng, Yuxuan Huang, Hongyang Jia, Jingyu Wang, Lu Zhang, Wenyu Sun, Huazhong Yang, Yongpan Liu:
An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 416-420 (2023)
[j68]
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Songming Yu, Yifan He, Hongyang Jia, Wenyu Sun, Mufeng Zhou, Luchang Lei, Wentao Zhao, Guofu Ma, Huazhong Yang, Yongpan Liu:
A Heterogeneous Microprocessor Based on All-Digital Compute-in-Memory for End-to-End AIoT Inference. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 3099-3103 (2023)
[c129]
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Yifan He, Haikang Diao, Chen Tang, Wenbin Jia, Xiyuan Tang, Yuan Wang, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu:
A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference. ISSCC 2023: 130-131
2014
[c24]
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Yiqun Wang, Hongyang Jia, Yongpan Liu, Qing'an Li, Chun Jason Xue, Huazhong Yang:
Register allocation for hybrid register architecture in nonvolatile processors. ISCAS 2014: 1050-1053
2012
[c16]
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  - conf/ipsn/LiuWJSWZZY12
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Yongpan Liu, Yiqun Wang, Hongyang Jia, Shan Su, Jinghuan Wen, Wenzhu Zhang, Lin Zhang, Huazhong Yang:
An energy harvesting nonvolatile sensor node and its application to distributed moving object detection. IPSN 2012: 149-150

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