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Srimat T. Chakradhar
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Publications
- 2015
- [c122]Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Approximate computing and the quest for computing efficiency. DAC 2015: 120:1-120:6 - [c121]Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Computing approximately, and efficiently. DATE 2015: 748-751 - 2014
- [j37]Vinay Kumar Chippa, Debabrata Mohapatra, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan:
Scalable Effort Hardware Design. IEEE Trans. Very Large Scale Integr. Syst. 22(9): 2004-2016 (2014) - [c119]Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Approximate computing for efficient information processing. ESTIMedia 2014: 9-10 - [c113]Faraz Ahmad, Srimat T. Chakradhar, Anand Raghunathan, T. N. Vijaykumar:
ShuffleWatcher: Shuffle-aware Scheduling in Multi-tenant MapReduce Clusters. USENIX Annual Technical Conference 2014: 1-12 - 2013
- [j35]Vinay K. Chippa, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan:
Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling. ACM Trans. Embed. Comput. Syst. 12(2s): 90:1-90:23 (2013) - [c111]Vinay K. Chippa, Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Approximate computing: An integrated hardware approach. ACSSC 2013: 111-117 - [c110]Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Analysis and characterization of inherent application resilience for approximate computing. DAC 2013: 113:1-113:9 - [c108]Swagath Venkataramani, Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Quality programmable vector processors for approximate computing. MICRO 2013: 1-12 - 2012
- [c106]Faraz Ahmad, Srimat T. Chakradhar, Anand Raghunathan, T. N. Vijaykumar:
Tarazu: optimizing MapReduce on heterogeneous clusters. ASPLOS 2012: 61-74 - [c103]Reza Farivar, Anand Raghunathan, Srimat T. Chakradhar, Harshit Kharbanda, Roy H. Campbell:
PIC: Partitioned Iterative Convergence for Clusters. CLUSTER 2012: 391-401 - [c98]Jacques A. Pienaar, Srimat T. Chakradhar, Anand Raghunathan:
Automatic generation of software pipelines for heterogeneous parallel systems. SC 2012: 24 - 2011
- [c95]Vinay K. Chippa, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar:
Dynamic effort scaling: managing the quality-efficiency tradeoff. DAC 2011: 603-608 - [c91]Jacques A. Pienaar, Anand Raghunathan, Srimat T. Chakradhar:
MDR: performance model driven runtime for heterogeneous parallel platforms. ICS 2011: 225-234 - 2010
- [c88]Surendra Byna, Jiayuan Meng, Anand Raghunathan, Srimat T. Chakradhar, Srihari Cadambi:
Best-effort semantic document search on GPUs. GPGPU 2010: 86-93 - [c87]Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar:
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. DAC 2010: 555-560 - [c86]Srimat T. Chakradhar, Anand Raghunathan:
Best-effort computing: re-thinking parallel software and hardware. DAC 2010: 865-870 - [c85]Jiayuan Meng, Anand Raghunathan, Srimat T. Chakradhar, Surendra Byna:
Exploiting the forgiving nature of applications for scalable parallel execution. IPDPS 2010: 1-12 - 2009
- [c80]Jiayuan Meng, Srimat T. Chakradhar, Anand Raghunathan:
Best-effort parallel execution framework for Recognition and mining applications. IPDPS 2009: 1-12 - [c79]Narayanan Sundaram, Anand Raghunathan, Srimat T. Chakradhar:
A framework for efficient and scalable execution of domain-specific templates on GPUs. IPDPS 2009: 1-12 - 2008
- [c78]Janar Thoguluva, Anand Raghunathan, Srimat T. Chakradhar:
Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor. DATE 2008: 1148-1153 - 2007
- [j30]Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar:
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 699-710 (2007) - 2006
- [j28]Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar:
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2193-2206 (2006) - [c69]Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar:
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. DAC 2006: 496-501 - 2005
- [c62]Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
SECA: security-enhanced communication architecture. CASES 2005: 78-89 - [c55]Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar:
Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. VLSI Design 2005: 65-70 - [c52]Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar:
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. VLSI Design 2005: 579-585 - 2004
- [c47]Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
Tamper Resistance Mechanisms for Secure, Embedded Systems. VLSI Design 2004: 605- - 2003
- [c43]Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
Embedding Security in Wireless Embedded Systems. VLSI Design 2003: 269-270 - [c42]Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
Efficient RTL Power Estimation for Large Designs. VLSI Design 2003: 431-439 - 2001
- [c41]Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar:
Accurate Power Macro-modeling Techniques for Complex RTL Circuits. VLSI Design 2001: 235-241 - 1997
- [j18]Srimat T. Chakradhar, Anand Raghunathan:
Bottleneck removal algorithm for dynamic compaction in sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10): 1157-1172 (1997) - 1996
- [c27]Anand Raghunathan, Srimat T. Chakradhar:
Dynamic test Sequence compaction for Sequential Circuits. VLSI Design 1996: 170-173 - 1995
- [c23]Srimat T. Chakradhar, Anand Raghunathan:
Bottleneck removal algorithm for dynamic compaction and test cycles reduction. EURO-DAC 1995: 98-104 - [c22]Anand Raghunathan, Srimat T. Chakradhar:
Acceleration techniques for dynamic vector compaction. ICCAD 1995: 310-317
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