Toshinori Suzuki

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Masahiro Kaminaga

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Publications

2020
[j16]
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Toshinori Suzuki, Masahiro Kaminaga:
A True Random Number Generator Method Embedded in Wireless Communication Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(4): 686-694 (2020)
2019
[j15]
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Masahiro Kaminaga, Toshinori Suzuki, Masaharu Fukase:
Determining the Optimal Random-Padding Size for Rabin Cryptosystems. IEEE Trans. Inf. Forensics Secur. 14(8): 2232-2242 (2019)
2018
[j14]
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Masahiro Kaminaga, Hideki Yoshikawa, Arimitsu Shikoda, Toshinori Suzuki:
Crashing Modulus Attack on Modular Squaring for Rabin Cryptosystem. IEEE Trans. Dependable Secur. Comput. 15(4): 723-728 (2018)
2016
[i2]
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Masahiro Kaminaga, Hideki Yoshikawa, Arimitsu Shikoda, Toshinori Suzuki:
Crashing Modulus Attack on Modular Squaring for Rabin Cryptosystem. CoRR abs/1603.00100 (2016)
2015
[j13]
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Masahiro Kaminaga, Hideki Yoshikawa, Toshinori Suzuki:
Double Counting in 2^t-ary RSA Precomputation Reveals the Secret Exponent. IEEE Trans. Inf. Forensics Secur. 10(7): 1394-1401 (2015)
2014
[j12]
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Hideki Yoshikawa, Masahiro Kaminaga, Arimitsu Shikoda, Toshinori Suzuki:
Round Addition DFA on SPN Block Ciphers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2671-2674 (2014)
[c20]
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Hideki Yoshikawa, Masahiro Kaminaga, Arimitsu Shikoda, Toshinori Suzuki:
Secret key reconstruction method using round addition DFA on lightweight block cipher LBlock. ISITA 2014: 493-496
[i1]
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Masahiro Kaminaga, Hideki Yoshikawa, Toshinori Suzuki:
Double Counting in $2^t$-ary RSA Precomputation Reveals the Secret Exponent. CoRR abs/1407.7598 (2014)
2013
[j11]
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Hideki Yoshikawa, Masahiro Kaminaga, Arimitsu Shikoda, Toshinori Suzuki:
Round Addition DFA on 80-bit Piccolo and TWINE. IEICE Trans. Inf. Syst. 96-D(9): 2031-2035 (2013)
[c19]
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  - conf/gcce/YoshikawaKSS13
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Hideki Yoshikawa, Masahiro Kaminaga, Arimitsu Shikoda, Toshinori Suzuki:
Round addition DFA for microcontroller implemented the triple DES. GCCE 2013: 538-539

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