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Tsutomu Yoshinaga

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Ben A. Abderazek

> Home > Persons > Tsutomu Yoshinaga

Publications

2020
[j31]
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  - journals/tetc/AhmedYA20
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  - https://dblp.org/rec/journals/tetc/AhmedYA20
Achraf Ben Ahmed, Tsutomu Yoshinaga, Abderazek Ben Abdallah:
Scalable Photonic Networks-on-Chip Architecture Based on a Novel Wavelength-Shifting Mechanism. IEEE Trans. Emerg. Top. Comput. 8(2): 533-544 (2020)
2008
[j7]
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  - journals/jpdc/AbderazekCYS08
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  - https://dblp.org/rec/journals/jpdc/AbderazekCYS08
Ben A. Abderazek, Arquimedes Canedo, Tsutomu Yoshinaga, Masahiro Sowa:
The QC-2 parallel Queue processor architecture. J. Parallel Distributed Comput. 68(2): 235-245 (2008)
2007
[c16]
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  dblp key:
  - conf/icppw/AbderazekAYS07
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  - https://dblp.org/rec/conf/icppw/AbderazekAYS07
Ben A. Abderazek, Mushfiquzzaman Akanda, Tsutomu Yoshinaga, Masahiro Sowa:
Mathematical Model for Multiobjective Synthesis of NoC Architectures. ICPP Workshops 2007: 36
2006
[j6]
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  - journals/tjs/AbderazekYS06
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Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa:
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. J. Supercomput. 38(1): 3-15 (2006)
[c15]
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  - conf/icppw/AbderazekYS06
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Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa:
Scalable Core-Based Methodology and Synthesizable Core for Systematic Design. ICPP Workshops 2006: 345-352
2005
[j5]
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  - journals/tjs/SowaAY05
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Masahiro Sowa, Ben A. Abderazek, Tsutomu Yoshinaga:
Parallel Queue Processor Architecture Based on Produced Order Computation Model. J. Supercomput. 32(3): 217-229 (2005)
[c14]
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  - conf/euc/AbderazekKYS05
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Ben A. Abderazek, Sotaro Kawata, Tsutomu Yoshinaga, Masahiro Sowa:
Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core. EUC 2005: 340-349
2003
[c12]
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  - conf/ispa/AbderazekSYS03
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Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa:
On the Design of a Register Queue Based Processor Architecture (FaRM-rq). ISPA 2003: 248-262
2002
[c9]
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  - conf/pdcs/SowaASNY02
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Masahiro Sowa, Ben A. Abderazek, Soichi Shigeta, Kirilka Nikolova, Tsutomu Yoshinaga:
Proposal and Design of a Parallel Queue Processor Architecture (PQP). IASTED PDCS 2002: 549-554

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