John P. Hayes

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Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
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Publications

2015
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John P. Hayes:
Introduction to stochastic computing and its challenges. DAC 2015: 59:1-59:3
2005
[c79]
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John P. Hayes:
Faults and Tests in Quantum Circuits. Asian Test Symposium 2005
2003
[c63]
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John P. Hayes:
Tutorial: basic concepts in quantum circuits. DAC 2003: 893
2002
[c55]
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John P. Hayes:
Fault-Tolerant Quantum Computers. IPDPS 2002
1987
[j29]
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John P. Hayes:
An Introduction to Switch-Level Modeling. IEEE Des. Test 4(4): 18-25 (1987)
1986
[j25]
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John P. Hayes:
Uncertainty, Energy, and Multiple-Valued Logics. IEEE Trans. Computers 35(2): 107-114 (1986)
[j24]
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John P. Hayes:
Pseudo-Boolean Logic Circuits. IEEE Trans. Computers 35(7): 602-612 (1986)
[j21]
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John P. Hayes:
Digital Simulation with Multiple Logic Values. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(2): 274-283 (1986)
1984
[j19]
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John P. Hayes:
Fault Modeling for Digital MOS Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(3): 200-208 (1984)
1982
[c4]
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John P. Hayes:
A fault simulation methodology for VLSI. DAC 1982: 393-399
1980
[j14]
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John P. Hayes:
Testing Memories for Single-Cell Pattern-Sensitive Faults. IEEE Trans. Computers 29(3): 249-254 (1980)
1978
[j12]
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John P. Hayes:
Generation of Optimal Transition Count Tests. IEEE Trans. Computers 27(1): 36-41 (1978)
[j11]
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John P. Hayes:
Path Complexity of Logic Networks. IEEE Trans. Computers 27(5): 459-462 (1978)
1976
[j10]
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John P. Hayes:
Enumeration of Fanout-Free Boolean Functions. J. ACM 23(4): 700-709 (1976)
[j9]
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John P. Hayes:
Transition Count Testing of Combinational Logic Circuits. IEEE Trans. Computers 25(6): 613-620 (1976)
[j8]
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John P. Hayes:
A Graph Model for Fault-Tolerant Computing Systems. IEEE Trans. Computers 25(9): 875-884 (1976)
[j7]
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John P. Hayes:
On the Properties of Irredundant Logic Networks. IEEE Trans. Computers 25(9): 884-892 (1976)
1975
[j6]
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John P. Hayes:
The Fanout Structure of Switching Functions. J. ACM 22(4): 551-571 (1975)
[j5]
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John P. Hayes:
Detection of Pattern-Sensitive Faults in Random-Access Memories. IEEE Trans. Computers 24(2): 150-157 (1975)
1974
[j4]
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John P. Hayes:
On Modifying Logic Networks to Improve Their Diagnosability. IEEE Trans. Computers 23(1): 56-62 (1974)
[c1]
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John P. Hayes:
Minimization of Fanout in Switching Networks. SWAT 1974: 133-139
1971
[j2]
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John P. Hayes:
A Nand Model ror Fault Diagnosis in Combinational Logic Networks. IEEE Trans. Computers 20(12): 1496-1506 (1971)
[j1]
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John P. Hayes:
On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests. IEEE Trans. Computers 20(12): 1506-1513 (1971)
1970
[b1]
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John Patrick Hayes:
A Study of Digital Network Structure and Its Relation to Fault Diagnosis. University of Illinois Urbana-Champaign, USA, 1970

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