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M. B. Srinivas
- > Home > Persons > M. B. Srinivas
Publications
- 2008
- [c48]J. V. R. Ravindra, M. B. Srinivas:
Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits. ACM Great Lakes Symposium on VLSI 2008: 111-114 - [c47]Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas:
Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects. ISQED 2008: 43-46 - 2007
- [j2]J. V. R. Ravindra, M. B. Srinivas:
Delay and Energy Efficient Coding Techniques for Capacitive Interconnects. J. Circuits Syst. Comput. 16(6): 929-942 (2007) - [c43]J. V. R. Ravindra, M. B. Srinivas:
A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects. DSD 2007: 325-330 - [c39]Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas:
Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects. ACM Great Lakes Symposium on VLSI 2007: 371-376 - [c38]Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas:
Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN). ISCAS 2007: 1129-1132 - [c35]K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas:
Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme. ISVLSI 2007: 401-408 - [c34]J. V. R. Ravindra, M. B. Srinivas:
Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs. Nano-Net 2007: 25 - [c31]K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas:
Bus encoding schemes for minimizing delay in VLSI interconnects. SBCCI 2007: 184-189 - [c30]J. V. R. Ravindra, Srinivas Bala Mandalika:
Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach. SBCCI 2007: 207-211 - 2006
- [c21]K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas:
Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method. DELTA 2006: 336-339 - [c18]K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas:
A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects. ISCAS 2006 - 2005
- [c5]K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas:
A novel deep submicron low power bus coding technique. Circuits, Signals, and Systems 2005: 154-159
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