Tobias G. Noll

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with coauthor community group 5

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Publications

2018
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Arne Heittmann, Tobias G. Noll:
Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cells. DATE 2018: 1496-1499
2017
[c77]
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Arne Heittmann, Tobias G. Noll:
Mixing circuit based on neural associative memories and nanoelectronic 1S1R cells. NANOARCH 2017: 119-124
2014
[c73]
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Arne Heittmann, Tobias G. Noll:
Variability analysis of a hybrid CMOS/RS nanoelectronic calibration circuit. ISCAS 2014: 1656-1659
2013
[c69]
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Arne Heittmann, Tobias G. Noll:
Modeling variability and irreproducibility of nanoelectronic resistive switches for circuit simulation. ASP-DAC 2013: 503-508
[c66]
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Arne Heittmann, Tobias G. Noll:
Variability evaluation of feedback circuits used in nanoelectronic Memristive/CMOS circuits. ACM Great Lakes Symposium on VLSI 2013: 137-142
[c65]
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Qin Wang, Arne Heittmann, Tobias G. Noll:
Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arrays. ACM Great Lakes Symposium on VLSI 2013: 233-238
2012
[c61]
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  - electronic edition @ esann.org (open access)
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Arne Heittmann, Tobias G. Noll:
A hybrid CMOS/memristive nanoelectronic circuit for programming synaptic weights. ESANN 2012
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Arne Heittmann, Tobias G. Noll:
Limits of writing multivalued resistances in passive nanoelectronic crossbars used in neuromorphic circuits. ACM Great Lakes Symposium on VLSI 2012: 227-232
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Arne Heittmann, Tobias G. Noll:
A Monte Carlo analysis of a write method used in passive nanoelectronic crossbars. NANOARCH 2012: 93-100
2011
[c52]
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Arne Heittmann, Tobias G. Noll:
Sensitivity of neuromorphic circuits using nanoelectronic resistive switches to pulse synchronization. ACM Great Lakes Symposium on VLSI 2011: 375-378

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