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Miroslav N. Velev
- > Home > Persons > Miroslav N. Velev
Publications
- 2005
- [j6]Miroslav N. Velev, Randal E. Bryant:
TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories. Int. J. Embed. Syst. 1(1/2): 134-149 (2005) - 2003
- [j3]Miroslav N. Velev, Randal E. Bryant:
Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors. J. Symb. Comput. 35(2): 73-106 (2003) - 2002
- [j2]Randal E. Bryant, Miroslav N. Velev:
Boolean satisfiability with transitivity constraints. ACM Trans. Comput. Log. 3(4): 604-627 (2002) - 2001
- [j1]Randal E. Bryant, Steven M. German, Miroslav N. Velev:
Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic. ACM Trans. Comput. Log. 2(1): 93-134 (2001) - [c16]Miroslav N. Velev, Randal E. Bryant:
EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality, and Conservative Transformations. CAV 2001: 235-240 - [c15]Miroslav N. Velev, Randal E. Bryant:
Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors. DAC 2001: 226-231 - 2000
- [c13]Randal E. Bryant, Miroslav N. Velev:
Boolean Satisfiability with Transitivity Constraints. CAV 2000: 85-98 - [c11]Miroslav N. Velev, Randal E. Bryant:
Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction. DAC 2000: 112-117 - [i2]Randal E. Bryant, Miroslav N. Velev:
Boolean Satisfiability with Transitivity Constraints. CoRR cs.LO/0008001 (2000) - 1999
- [c10]Randal E. Bryant, Steven M. German, Miroslav N. Velev:
Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions. CAV 1999: 470-482 - [c9]Miroslav N. Velev, Randal E. Bryant:
Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic. CHARME 1999: 37-53 - [c8]Miroslav N. Velev, Randal E. Bryant:
Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors. DAC 1999: 397-401 - [c7]Randal E. Bryant, Steven M. German, Miroslav N. Velev:
Microprocessor Verification Using Efficient Decision Procedures for a Logic of Equality with Uninterpreted Functions. TABLEAUX 1999: 1-13 - [i1]Randal E. Bryant, Steven M. German, Miroslav N. Velev:
Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic. CoRR cs.LO/9910014 (1999) - 1998
- [c6]Miroslav N. Velev, Randal E. Bryant:
Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation. ACSD 1998: 200-212 - [c5]Miroslav N. Velev, Randal E. Bryant:
Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking. FMCAD 1998: 18-35 - [c4]Miroslav N. Velev, Randal E. Bryant:
Incorporating timing constraints in the efficient memory model for symbolic ternary simulation. ICCD 1998: 400-406 - [c3]Miroslav N. Velev, Randal E. Bryant:
Efficient Modeling of Memory Arrays in Symbolic Ternary Simulation. TACAS 1998: 136-150 - 1997
- [c2]Randal E. Bryant, Miroslav N. Velev:
Verification of Pipelined Microprocessors by Comparing Memory Execution Sequences in Symbolic Simulation. ASIAN 1997: 18-31 - [c1]Miroslav N. Velev, Randal E. Bryant, Alok Jain:
Efficient Modeling of Memory Arrays in Symbolic Simulation. CAV 1997: 388-399
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