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Jer-Min Jou
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Publications
- 2004
- [j11]Yeu-Horng Shiau, Jer-Min Jou, Chin-Chi Liu:
Efficient Architectures for the Biorthogonal Wavelet Transform by Filter Bank and Lifting Scheme. IEICE Trans. Inf. Syst. 87-D(7): 1867-1877 (2004) - 2002
- [j10]Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, Ren-Der Chen:
Design of a dynamic pipelined architecture for fuzzy color correction. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 924-929 (2002) - 2001
- [j9]Pei-Yin Chen, Jer-Min Jou:
An efficient blocking-matching algorithm based on fuzzy reasoning. IEEE Trans. Syst. Man Cybern. Part B 31(2): 253-259 (2001) - [c12]Jer-Min Jou, Yeu-Horng Shiau, Chen-Jen Huang:
An efficient VLSI architecture for HMM-based speech recognition. ICECS 2001: 469-472 - [c11]Jer-Min Jou, Yeu-Horng Shiau, Chin-Chi Liu:
Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme. ISCAS (2) 2001: 529-532 - 2000
- [j8]Pei-Yin Chen, Jer-Min Jou:
Adaptive arithmetic coding using fuzzy reasoning and grey prediction. Fuzzy Sets Syst. 114(2): 239-254 (2000) - [j7]Jer-Min Jou, Pei-Yin Chen, Sheng-Fu Yang:
An adaptive fuzzy logic controller: its VLSI architecture and applications. IEEE Trans. Very Large Scale Integr. Syst. 8(1): 52-60 (2000) - 1999
- [j6]Jer-Min Jou, Pei-Yin Chen:
A fast and efficient lossless data-compression method. IEEE Trans. Commun. 47(9): 1278-1283 (1999) - [j5]Jer-Min Jou, Pei-Yin Chen, Jian-Ming Sun:
The gray prediction search algorithm for block motion estimation. IEEE Trans. Circuits Syst. Video Technol. 9(6): 843-848 (1999) - [c10]Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau:
Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. ASP-DAC 1999: 185-188 - [c9]Jer-Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Ming-Shiang Liang:
A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform. ASP-DAC 1999: 205-208 - [c8]Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau:
A New Pipelined Architecture for Fuzzy Color Correction. ASP-DAC 1999: 209- - [c7]Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau:
An efficient method for the decomposition and resynthesis of speed-independent circuits. ICECS 1999: 339-342 - [c6]Jer-Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Jian-Ming Sun:
A grey prediction motion estimator for digital image processing. ICECS 1999: 701-704 - 1997
- [j4]Shung-Chih Chen, Jer-Min Jou:
Serial diagnostic fault simulation for synchronous sequential circuits. Integr. 23(2): 157-170 (1997) - [j3]Shung-Chih Chen, Jer-Min Jou:
Diagnostic fault simulation for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(3): 299-308 (1997) - 1995
- [c5]Jer-Min Jou, Shung-Chih Chen:
Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning. ISCAS 1995: 2004-2007 - 1994
- [c4]Jer-Min Jou, Shung-Chih Chen:
A fast and memory-efficient diagnostic fault simulation for sequential circuits. ICCAD 1994: 723-726 - [c3]Jer-Min Jou, Ren-Der Chen, Shiann-Rong Kuang:
Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization. ISCAS 1994: 45-48 - [c2]Jer-Min Jou, Shung-Chih Chen, Ren-Der Chen:
A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits. ISCAS 1994: 85-88 - 1993
- [c1]Jer-Min Jou, Shiann-Rong Kuang:
Library-Adaptively Integrated Data Path Synthesis for DSP Systems. ICCD 1993: 379-382
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