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Sotirios G. Ziavras
- > Home > Persons > Sotirios G. Ziavras
Publications
- 2015
- [j46]Khondaker Musfakus Salehin, Roberto Rojas-Cessa, Sotirios G. Ziavras:
A Method to Measure Packet Processing Time of Hosts Using High-Speed Transmission Lines. IEEE Syst. J. 9(4): 1248-1251 (2015) - [j45]Spiridon F. Beldianu, Sotirios G. Ziavras:
Performance-Energy Optimizations for Shared Vector Accelerators in Multicores. IEEE Trans. Computers 64(3): 805-817 (2015) - 2014
- [c55]Spiridon F. Beldianu, Sotirios G. Ziavras:
ASIC Design of Shared Vector Accelerators for Multicore Processors. SBAC-PAD 2014: 182-189 - 2013
- [j44]Spiridon F. Beldianu, Sotirios G. Ziavras:
Multicore-based vector coprocessor sharing for performance and energy gains. ACM Trans. Embed. Comput. Syst. 13(2): 17:1-17:25 (2013) - [c54]Shashank Suresh, Spiridon F. Beldianu, Sotirios G. Ziavras:
FPGA and ASIC square root designs for high performance and power efficiency. ASAP 2013: 269-272 - [c53]Nitesh B. Guinde, Roberto Rojas-Cessa, Sotirios G. Ziavras:
Packet classification using rule caching. IISA 2013: 1-6 - [c52]Spiridon F. Beldianu, Sotirios G. Ziavras:
Efficient on-chip vector processing for multicore processors. ISSoC 2013: 1-4 - 2012
- [j42]Spiridon F. Beldianu, Christopher Dahlberg, Timothy Steele, Sotirios G. Ziavras:
Versatile design of shared vector coprocessors for multicores. Microprocess. Microsystems 36(7): 543-554 (2012) - 2011
- [c50]Spiridon F. Beldianu, Sotirios G. Ziavras:
On-chip Vector Coprocessor Sharing for Multicores. PDP 2011: 431-438 - 2010
- [j39]Nitesh B. Guinde, Sotirios G. Ziavras:
Efficient hardware support for pattern matching in network intrusion detection. Comput. Secur. 29(7): 756-769 (2010) - [j38]Spiridon F. Beldianu, Roberto Rojas-Cessa, Eiji Oki, Sotirios G. Ziavras:
Scheduling for input-queued packet switches by a re-configurable parallel match evaluator. IEEE Commun. Lett. 14(4): 357-359 (2010) - [c46]Nitesh B. Guinde, Sotirios G. Ziavras:
Novel FPGA-Based Signature Matching for Deep Packet Inspection. WISTP 2010: 261-276 - 2009
- [c42]Spiridon F. Beldianu, Roberto Rojas-Cessa, Eiji Oki, Sotirios G. Ziavras:
Re-Configurable Parallel Match Evaluators Applied to Scheduling Schemes for Input-Queued Packet Switches. ICCCN 2009: 1-6 - 2007
- [c36]Kanchan Devarakonda, Sotirios G. Ziavras, Roberto Rojas-Cessa:
Measuring Network Parameters with Hardware Support. ICNS 2007: 2 - 2005
- [c22]Roberto Rojas-Cessa, Ziqian Dong, Sotirios G. Ziavras:
Load-balanced CICB packet switch with support for long round-trip times. GLOBECOM 2005: 5 - 2000
- [j16]Sotirios G. Ziavras, Haim Grebel, Anthony T. Chronopoulos, Florent Marcelli:
A new-generation parallel computer and its performance evaluation. Future Gener. Comput. Syst. 17(3): 315-333 (2000)
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