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Edwin Naroska
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Publications
- 2024
- [j9]Chun-Yi Lin, Muhamad Amirul Haq, Jiunhan Chen, Shanq-Jang Ruan, Edwin Naroska:
Efficient Saliency Map Detection for Low-Light Images Based on Image Gradient. IEEE Trans. Circuits Syst. Video Technol. 34(2): 852-865 (2024) - 2018
- [j8]Chih-Wei Lee, Peter Chondro, Shanq-Jang Ruan, Oliver Christen, Edwin Naroska:
Improving Mobility for the Visually Impaired: A Wearable Indoor Positioning System Based on Visual Markers. IEEE Consumer Electron. Mag. 7(3): 12-20 (2018) - [c29]Edwin Naroska, Sebastian Schmitz, Tobias Bolten, Chih-Wei Lee, Ping-Chen Tsai, Shanq-Jang Ruan:
Project OurPuppet: A system to support people with dementia and their caregiving relatives at home. ICCE 2018: 1-4 - 2016
- [c25]Yu-Chang Huang, Shanq-Jang Ruan, Oliver Christen, Edwin Naroska:
A wearable indoor locating system based on visual marker recognition for people with visual impairment. GCCE 2016: 1-2 - 2010
- [c23]Kai-Ti Hu, Yu-Ting Pai, Shanq-Jang Ruan, Edwin Naroska:
A hardware-efficient color segmentation algorithm for face detection. APCCAS 2010: 688-691 - 2009
- [c21]Yu-Ting Pai, Chia-Han Lee, Shanq-Jang Ruan, Edwin Naroska:
An improved comparison circuit for low power pre-computation-based content-addressable memory designs. ICECS 2009: 663-666 - 2006
- [j7]Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn:
Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing. IEEE Trans. Very Large Scale Integr. Syst. 14(4): 421-425 (2006) - [c17]Jörg Platte, Edwin Naroska, Kai Grundmann:
A Cache Design for a Security Architecture for Microprocessors (SAM). ARCS 2006: 435-449 - [c16]Jörg Platte, Raúl Durán Díaz, Edwin Naroska:
A New Encryption and Hashing Scheme for the Security Architecture for Microprocessors. Communications and Multimedia Security 2006: 120-129 - [c15]Jörg Platte, Raúl Durán Díaz, Edwin Naroska:
An Operating System Design for the Security Architecture for Microprocessors. ICICS 2006: 174-189 - [c14]Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen:
Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs. ISPD 2006: 114-119 - 2005
- [j6]Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai:
Bipartitioning and encoding in low-power pipelined circuits. ACM Trans. Design Autom. Electr. Syst. 10(1): 24-32 (2005) - [c13]Jörg Platte, Edwin Naroska:
A combined hardware and software architecture for secure computing. Conf. Computing Frontiers 2005: 280-288 - [c12]Uwe Schwiegelshohn, Edwin Naroska:
Verlustleistungsarme Fehlerschutzprotokolle basierend auf punktierten Low Density Parity Check Codes (LDPC). GI Jahrestagung (1) 2005: 461 - [c11]Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn:
Simultaneous Wire Permutation, Inversion, and Spacing with Genetic Algorithm for Energy-Efficient Bus Design. IPDPS 2005 - [c10]Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn:
An efficient algorithm for simultaneous wire permutation, inversion, and spacing. ISCAS (1) 2005: 109-112 - 2004
- [j5]Peter Schramm, Edwin Naroska, Peter Resch, Jörg Platte, Holger Linde, Guido Stromberg, Thomas F. Sturm:
A Service Gateway for Networked Sensor Systems. IEEE Pervasive Comput. 3(1): 66-74 (2004) - [c9]Uwe Dammer, Edwin Naroska, Stefan Schmermbeck, Uwe Schwiegelshohn:
A data puncturing IR-scheme for type-II hybrid ARQ protocols using LDPC codes. GLOBECOM 2004: 3012-3016 - [c8]Yvonne Gsottberger, Xiaolei Shi, Guido Stromberg, Werner Weber, Thomas F. Sturm, Holger Linde, Edwin Naroska, Peter Schramm:
Sindrion: a prototype system for low-power wireless control networks. MASS 2004: 513-515 - 2003
- [c7]Edwin Naroska, Shanq-Jang Ruan, Chia-Lin Ho, Said Mchaalia, Feipei Lai, Uwe Schwiegelshohn:
A novel approach for digital waveform compression. ASP-DAC 2003: 712-715 - [c6]Edwin Naroska, Shanq-Jang Ruan, Feipei Lai, Uwe Schwiegelshohn, Le-Chin Liu:
On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms. ISCAS (5) 2003: 277-280 - 2002
- [j4]Edwin Naroska, Uwe Schwiegelshohn:
On an on-line scheduling problem for parallel jobs. Inf. Process. Lett. 81(6): 297-304 (2002) - [j3]Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn:
ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 942-949 (2002) - [c5]Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Chia-Lin Ho, Feipei Lai:
Energy analysis of bipartition architecture for pipelined circuits. APCCAS (2) 2002: 7-11 - [c4]Shanq-Jang Ruan, Edwin Naroska, Chia-Lin Ho, Feipei Lai:
Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits. ICCD 2002: 327- - 2001
- [j2]Edwin Naroska, Feipei Lai, Rung-Ji Shang, Uwe Schwiegelshohn:
Efficient parallel timing simulation of synchronous models on networks of workstations. J. Syst. Archit. 47(6): 517-528 (2001) - 2000
- [c3]Edwin Naroska, Rung-Ji Shang, Feipei Lai, Uwe Schwiegelshohn:
Hybrid Parallel Circuit Simulation Approaches. IEEE PACT 2000: 261-270 - 1999
- [j1]Edwin Naroska, Uwe Schwiegelshohn:
Conservative Parallel Simulation of a Large Number of Processes. Simul. 72(3): 150-162 (1999) - 1996
- [c1]Edwin Naroska, Uwe Schwiegelshohn:
A New Scheduling Method for Parallel Discrete-Event Simulation. Euro-Par, Vol. II 1996: 582-593
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last updated on 2024-03-02 02:42 CET by the dblp team
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