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David W. Matula
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Publications
- 2013
- [c65]Jason Moore, Mitchell A. Thornton, David W. Matula:
Low power floating-point multiplication and squaring units with shared circuitry. MWSCAS 2013: 1395-1398 - 2009
- [j29]Alex Fit-Florea, Lun Li, Mitchell A. Thornton, David W. Matula:
A Discrete Logarithm Number System for Integer Arithmetic Modulo 2k: Algorithms and Lookup Structures. IEEE Trans. Computers 58(2): 163-174 (2009) - [c59]Satyendra R. Datla, Mitchell A. Thornton, David W. Matula:
A Low Power High Performance Radix-4 Approximate Squaring Circuit. ASAP 2009: 91-97 - 2008
- [c57]Jason Moore, Mitchell A. Thornton, David W. Matula:
A low power radix-4 dual recoded integer squaring implementation for use in design of application specific arithmetic circuits. ACSCC 2008: 1819-1822 - [c55]Mitchell A. Thornton, David W. Matula, Laura Spenner, D. Michael Miller:
Quantum Logic Implementation of Unary Arithmetic Operations. ISMVL 2008: 202-207 - 2006
- [c54]Lun Li, Alex Fit-Florea, Mitchell A. Thornton, David W. Matula:
Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer Functions. ASAP 2006: 99-104 - [c53]David W. Matula, Lee D. McFearin:
A formal model and efficient traversal algorithm for generating testbenches for verification of IEEE standard floating point division. DATE 2006: 1134-1138 - [c52]Lun Li, Mitchell A. Thornton, David W. Matula:
A digit serial algorithm for the integer power operation. ACM Great Lakes Symposium on VLSI 2006: 302-307 - 2005
- [j27]Peter-Michael Seidel, Lee D. McFearin, David W. Matula:
Secondary Radix Recodings for Higher Radix Multipliers. IEEE Trans. Computers 54(2): 111-123 (2005) - [c51]Alex Fit-Florea, David W. Matula:
Determining all pairs edge connectivity of a 4-regular graph in O(|V|). AICCSA 2005: 15 - [c50]David W. Matula, Alex Fit-Florea, Mitchell Aaron Thornton:
Table Lookup Structures for Multiplicative Inverses Modulo 2k. IEEE Symposium on Computer Arithmetic 2005: 156-163 - [c49]Peter Kornerup, David W. Matula:
Single Precision Reciprocals by Multipartite Table Lookup. IEEE Symposium on Computer Arithmetic 2005: 240-248 - [c48]Lun Li, Alex Fit-Florea, Mitchell A. Thornton, David W. Matula:
Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2k. ISVLSI 2005: 130-135 - 2004
- [c47]Alex Fit-Florea, David W. Matula:
A Digit-Serial Algorithm for the Discrete Logarithm Modulo 2k. ASAP 2004: 236-246 - 2003
- [j26]David W. Matula, Lee D. McFearin:
A p×p bit fraction model of binary floating point division and extremal rounding cases. Theor. Comput. Sci. 291(2): 159-182 (2003) - [j25]Marc Daumas, David W. Matula:
Further Reducing the Redundancy of a Notation Over a Minimally Redundant Digit Set. J. VLSI Signal Process. 33(1-2): 7-18 (2003) - [c45]David W. Matula, Alex Fit-Florea:
Prescaled Integer Division. IEEE Symposium on Computer Arithmetic 2003: 63- - 2002
- [c44]David W. Matula, Alex Fit-Florea, Lee D. McFearin:
Evaluating Products of Non Linear Functions by Indirect Bipartite Table Lookup. ASAP 2002: 120-129 - 2001
- [c43]Peter-Michael Seidel, Lee D. McFearin, David W. Matula:
Binary Multiplication Radix-32 and Radix-256. IEEE Symposium on Computer Arithmetic 2001: 23-32 - [c41]Lee D. McFearin, David W. Matula:
Generation and Analysis of Hard to Round Cases for Binary Floating Point Division. IEEE Symposium on Computer Arithmetic 2001: 119-127 - [c40]Lee D. McFearin, David W. Matula:
Selecting A Well Distributed Hard Case Test Suite for IEEE Standard Floating Point Division. ICCD 2001: 89-97 - 2000
- [j22]Asger Munk Nielsen, David W. Matula, Chung Nan Lyu, Guy Even:
An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm. IEEE Trans. Computers 49(1): 33-47 (2000) - [j21]Milos D. Ercegovac, Laurent Imbert, David W. Matula, Jean-Michel Muller, Guoheng Wei:
Improving Goldschmidt Division, Square Root, and Square Root Reciprocal. IEEE Trans. Computers 49(7): 759-763 (2000) - [c39]Marc Daumas, David W. Matula:
A Booth Multiplier Accepting Both a Redundant or a Non-Redundant Input with No Additional Delay. ASAP 2000: 205-214 - 1997
- [j20]Marc Daumas, David W. Matula:
Validated Roundings of Dot Products by Sticky Accumulation. IEEE Trans. Computers 46(5): 623-629 (1997) - [c32]David W. Matula, Asger Munk Nielsen:
Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder. IEEE Symposium on Computer Arithmetic 1997: 140-147 - [c31]Asger Munk Nielsen, David W. Matula, Chung Nan Lyu, Guy Even:
Pipelined Packet-Forwarding Floating Point: II. An Adder. IEEE Symposium on Computer Arithmetic 1997: 148-155 - 1995
- [j19]Peter Kornerup, David W. Matula:
LCF: A Lexicagraphic Binary representation of the Rationals. J. Univers. Comput. Sci. 1(7): 484-503 (1995) - [c29]Chung Nan Lyu, David W. Matula:
Redundant Binary Booth Recoding. IEEE Symposium on Computer Arithmetic 1995: 50- - 1993
- [c28]Marc Daumas, David W. Matula:
Design of a fast validated dot product operation. IEEE Symposium on Computer Arithmetic 1993: 62-69 - 1991
- [c23]Gerd Bohlender, Wolfgang Walter, Peter Kornerup, David W. Matula:
Semantics for exact floating point operations. IEEE Symposium on Computer Arithmetic 1991: 22-26 - 1990
- [j15]Peter Kornerup, David W. Matula:
An Algorithm for Redundant Binary Bit-Pipelined Rational Arithmetic. IEEE Trans. Computers 39(8): 1106-1115 (1990) - 1989
- [c20]Peter Kornerup, David W. Matula:
Exploiting redundancy in bit-pipelined rational arithmetic. IEEE Symposium on Computer Arithmetic 1989: 119-126 - 1988
- [j14]Peter Kornerup, David W. Matula:
An On-Line Arithmetic Unit for Bit-Pipelined Rational Arithmetic. J. Parallel Distributed Comput. 5(3): 310-330 (1988) - 1987
- [c18]Peter Kornerup, David W. Matula:
A bit-serial arithmetic unit for rational arithmetic. IEEE Symposium on Computer Arithmetic 1987: 204-211 - 1985
- [j12]David W. Matula, Peter Kornerup:
Finite Precision Rational Arithmetic Slash Number Systems. IEEE Trans. Computers 34(1): 3-18 (1985) - [c15]Peter Kornerup, David W. Matula:
Finite precision lexicographic continued fraction number systems. IEEE Symposium on Computer Arithmetic 1985: 207-213 - 1983
- [j9]Peter Kornerup, David W. Matula:
Finite Precision Rational Arithmetic: An Arithmetic Unit. IEEE Trans. Computers 32(4): 378-388 (1983) - [c14]David W. Matula, Peter Kornerup:
An order preserving finite binary encoding of the rationals. IEEE Symposium on Computer Arithmetic 1983: 201-209 - 1981
- [c13]Peter Kornerup, David W. Matula:
An integrated rational arithmetic unit. IEEE Symposium on Computer Arithmetic 1981: 233-240 - 1979
- [c12]David W. Matula, Peter Kornerup:
An approximate rational arithmetic system with intrinsic recovery of simple fractions during expression evaluation. EUROSAM 1979: 383-397 - 1978
- [c10]David W. Matula, Peter Kornerup:
A feasibility analysis of binary fixed-slash and floating-slash number systems. IEEE Symposium on Computer Arithmetic 1978: 29-38 - [c9]Peter Kornerup, David W. Matula:
A feasibility analysis of fixed-slash rational arithmetic. IEEE Symposium on Computer Arithmetic 1978: 39-47 - 1975
- [e1]T. R. N. Rao, David W. Matula:
3rd IEEE Symposium on Computer Arithmetic, ARITH 1975, Dallas, TX, USA, November 19-20, 1975. IEEE Computer Society 1975 [contents]
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