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Hiroyuki Kawai
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Publications
- 2018
- [j19]Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Yasumitsu Murai, Sugako Otani, Koji Nii, Yoshio Matsuda, Hiroyuki Kondo:
Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications. IEEE Trans. Multi Scale Comput. Syst. 4(4): 784-792 (2018) - 2017
- [c49]Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Koji Nii, Hiroyuki Kondo:
Low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications. COOL Chips 2017: 1-3 - 2016
- [c48]Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Hiroyuki Kondo:
Low-power multi-sensor system with normally-off sensing technology for IoT applications. ISOCC 2016: 195-196 - 2014
- [j18]Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. IEICE Trans. Electron. 97-C(4): 332-341 (2014) - [c42]Masanori Hayashikoshi, Yohei Sato, Hiroshi Ueki, Hiroyuki Kawai, Toru Shimizu:
Normally-off MCU architecture for low-power sensor node. ASP-DAC 2014: 12-16 - [c41]Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. ISQED 2014: 16-23 - 2013
- [j17]Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai:
A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. IEEE J. Solid State Circuits 48(11): 2671-2680 (2013) - 2012
- [c33]Hidehiro Fujiwara, Makoto Yabuuchi, Yasumasa Tsukamoto, Hirofumi Nakano, Toru Owada, Hiroyuki Kawai, Koji Nii:
A stable chip-ID generating physical uncloneable function using random address errors in SRAM. SoCC 2012: 143-147 - 2010
- [c27]Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto:
Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. SoCC 2010: 519-524 - 1995
- [j1]Kazunari Inoue, Hisashi Nakamura, Hiroyuki Kawai:
A 10 Mb frame buffer memory with Z-compare and A-blend units. IEEE J. Solid State Circuits 30(12): 1563-1568 (1995) - [c2]Hiroyuki Kawai, Yoshitugu Inoue, Robert Streitenberger, Masahiko Yoshimoto:
A highly-parallel DSP architecture for image recognition. ICASSP 1995: 3199-3202
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