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Cheng-Wen Wu
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Publications
- 2018
- [c146]Ying-Cih Kao, Cheng-Wen Wu:
A Self-Organizing Map-Based Adaptive Traffic Light Control System with Reinforcement Learning. ACSSC 2018: 2060-2064 - [c143]Su-Fu Kuo, Cheng-Wen Wu:
Symbiotic Controller Design Using a Memory-Based FSM Model. ISIE 2018: 874-879 - 2001
- [c38]Ching-Hong Tsai, Cheng-Wen Wu:
Processor-programmable memory BIST for bus-connected embedded memories. ASP-DAC 2001: 325-330 - 2000
- [j28]Kun-Jin Lin, Cheng-Wen Wu:
A Low-Power CAM Design for LZ Data Compression. IEEE Trans. Computers 49(10): 1139-1145 (2000) - [j27]Kun-Jin Lin, Cheng-Wen Wu:
Testing content-addressable memories using functional fault modelsand march-like algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5): 577-588 (2000) - 1998
- [j18]Yeong-Ruey Shieh, Cheng-Wen Wu:
Control and Observation Structures for Analog Circuits. IEEE Des. Test Comput. 15(2): 56-64 (1998) - [j16]Yeong-Ruey Shieh, Cheng-Wen Wu:
Design of CMOS PSCD Circuits and Checkers for Stuck-At and Stuck-On Faults. VLSI Design 5(4): 357-372 (1998) - [c12]Yu-Chun Chuang, Cheng-Wen Wu:
On-Line Error Detection Schemes for a Systolic Finite-Field Inverter. Asian Test Symposium 1998: 301-305 - 1997
- [j15]Kun-Jin Lin, Cheng-Wen Wu:
Practical Realization of Multiple-Input Exclusive-OR Circuits for Low-Power Applications. J. Circuits Syst. Comput. 7(1): 31-48 (1997) - 1995
- [j11]Yih-Lang Li, Cheng-Wen Wu:
Cellular automata for efficient parallel logic and fault simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6): 740-749 (1995) - [j9]Cheng-Wen Wu, Ming-Kwang Chang:
Bit-level systolic arrays for finite-field multiplications. J. VLSI Signal Process. 10(1): 85-92 (1995) - [c6]Yeong-Ruey Shieh, Cheng-Wen Wu:
DC control and observation structures for analog circuits. Asian Test Symposium 1995: 120-126 - 1994
- [j8]Shih-Yuang Su, Cheng-Wen Wu:
Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns. IEEE Trans. Computers 43(4): 495-501 (1994) - [c5]Yih-Lang Li, Cheng-Wen Wu:
Logic and Fault Simulation by Cellular Automata. EDAC-ETC-EUROASIC 1994: 552-556 - 1993
- [j7]Cheng-Wen Wu, Jiann-Yuan Choue:
Fault-Tolerant FFT Butterfly Network Design. J. Inf. Sci. Eng. 9(1): 137-150 (1993) - 1991
- [j6]Kun-Jin Lin, Cheng-Wen Wu:
Easily Testable Cellular Array Multipliers. J. Inf. Sci. Eng. 7(3): 367-383 (1991) - 1990
- [j3]Cheng-Wen Wu, Peter R. Cappello:
Easily Testable Iterative Logic Arrays. IEEE Trans. Computers 39(5): 640-652 (1990) - 1988
- [j2]Cheng-Wen Wu, Peter R. Cappello:
Application-specific CAD of VLSI second-order sections. IEEE Trans. Acoust. Speech Signal Process. 36(5): 813-825 (1988) - 1987
- [j1]Peter R. Cappello, Cheng-Wen Wu:
Computer-aided design of VLSI FIR filters. Proc. IEEE 75(9): 1260-1271 (1987) - [c2]Cheng-Wen Wu, Peter R. Cappello:
Application-Specific CAD of High-Throughout IIR Filters. COMPCON 1987: 302-305 - [c1]Cheng-Wen Wu, Peter R. Cappello:
Computer-aided design of VLSI second-order sections. ICASSP 1987: 1907-1910
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