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Thomas A. Ziaja
2010 – today
- 2012
[j2]Manish Shah, Robert T. Golla, Greg Grohoski, Paul J. Jordan, Jama Barreh, Jeffrey Brooks, Mark Greenberg, Gideon Levinsky, Mark Luttrell, Christopher Olson, Zeid Samoail, Matt Smittle, Thomas A. Ziaja: Sparc T4: A Dynamically Threaded Server-on-a-Chip. IEEE Micro 32(2): 8-19 (2012)
2000 – 2009
- 2009
- [c6]
- 2008
- [c5]Liang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen: Transition Test on UltraSPARC- T2 Microprocessor. ITC 2008: 1-10
- 2007
- [c4]Robert F. Molyneaux, Thomas A. Ziaja, Hong Kim, Shahryar Aryani, Sungbae Hwang, Alex Hsieh: Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip. ITC 2007: 1-8
- 2002
- [c3]Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar: A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors. ITC 2002: 726-735
- 2001
- [c2]Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar: Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. ICCD 2001: 526-529
1990 – 1999
- 1999
- [c1]
- 1994
- [j1]Thomas A. Ziaja, Earl E. Swartzlander Jr.: Boundary scan in board manufacturing. J. Electronic Testing 5(2-3): 263-268 (1994)
Coauthor Index
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last updated on 2012-09-10 15:51 CEST by the dblp team