Huafeng Yu

Yue Ma, Huafeng Yu, Thierry Gautier, Paul Le Guernic, Jean-Pierre Talpin, Loïc Besnard, Maurice Heitz: Toward polychronous analysis and validation for timed software architectures in AADL. DATE 2013: 1173-1178

Huafeng Yu, Jean-Pierre Talpin, Loïc Besnard, Thierry Gautier, Hervé Marchand, Paul Le Guernic: Polychronous controller synthesis from MARTE CCSL timing specifications. MEMOCODE 2011: 21-30

Huafeng Yu, Yue Ma, Yann Glouche, Jean-Pierre Talpin, Loïc Besnard, Thierry Gautier, Paul Le Guernic, Andres Toom, Odile Laurent: System-level co-simulation of integrated avionics using polychrony. SAC 2011: 354-359

Imran Rafiq Quadri, Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Samy Meftali, Jean-Luc Dekeyser: Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation. IJES 4(3/4): 204-224 (2010)

Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser: Model-Driven Engineering and Formal Validation of High-Performance Embedded Systems. Scalable Computing: Practice and Experience 10(2) (2009)

Abdoulaye Gamatié, Huafeng Yu, Gwenaël Delaval, Éric Rutten: A Case Study on Controller Synthesis for Data-Intensive Embedded Systems. ICESS 2009: 75-82

Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser: Synchronous Modeling and Analysis of Data Intensive Applications. EURASIP J. Emb. Sys. 2008 (2008)

Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser: Safe design of high-performance embedded systems in an MDE framework. ISSE 4(3): 215-222 (2008)

Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser: Modeling and Formal Validation of High-Performance Embedded Systems. ISPDC 2008: 215-222

Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser: Model Transformations from a Data Parallel Formalism towards Synchronous Languages. FDL 2007: 255-260

Alain Girault, Huafeng Yu: A flexible method to tolerate value sensor failures. ETFA 2006: 86-93